1.1. F-Tile CPRI PHY Multirate Intel® FPGA IP v2.1.0
Intel® Quartus® Prime Pro Edition Version | Description | Impact |
---|---|---|
22.1 | Removed support for ModelSim* SE simulator. | — |
Added new parameter: Enable CDR Clock Output. | — |
Intel® Quartus® Prime Pro Edition Version | Description | Impact |
---|---|---|
22.1 | Removed support for ModelSim* SE simulator. | — |
Added new parameter: Enable CDR Clock Output. | — |