F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 10/20/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Precision Time Protocol Interface
2.15. Precision Time Protocol Interface x
2.15.1. PTP Clock Interface 2.15.2. Time-of-Day Interface 2.15.3. TX 2-Step Timestamp Interface 2.15.4. TX 1-Step Timestamp Interface 2.15.5. RX Timestamp Interface 2.15.6. PTP Status Interface 2.15.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

6. Configuration Registers

You can access the registers for the F-Tile Ethernet Multirate Intel FPGA IP core using the Avalon® memory-mapped interface or the Ethernet reconfiguration Avalon® memory-mapped interface.
The control status register (CSR) space of all ports is always accessible regardless of whether the port is active. The dynamic reconfiguration (DR)-related registers are used for switching profiles within a reconfiguration group. The DR registers are only available in the port 0 CSR space.
Note: In a multiple port profile, the port 0 Avalon® memory-mapped interface space is available even if the port 0 is in reset. This is due to the fact that the i_reconfig_reset signal is a common reset for the entire F-Tile Ethernet Multirate IP core.
The table describes F-Tile Ethernet Multirate IP core specific registers. Refer to F-Tile Ethernet Intel® FPGA Hard IP User Guide for description of additional Ethernet-related registers.
Table 77.  F-Tile Ethernet Multirate IP Core Registers
Offset (Byte) Name Description Default Setting
0x200 8 profile_sel[5:0] Profile Selection Register
profile_sel[5:0] = {profile_sel[5:4], profile_sel[3:2], profile_sel[1:0]}, where
  • profile_sel[5:4]: Indicates the number of active ports in a selected profile:
    • 2'b00: 1 port
    • 2'b01: 2 port
    • 2'b10: 4 port
  • profile_sel[3:2]: Indicates the number of active transceiver lanes in a selected profile:
    • 2'b00: Maximum number of lanes in reconfiguration group
    • 2'b01: Maximum number of lanes /2 in reconfiguration group
    • 2'b10: Maximum number of lanes /4 in reconfiguration group
  • profile_sel1:0]: Indicates the sum of bandwidth of all active ports in a selected profile:
    • 2'b00: Maximum bandwidth (BW) in reconfiguration group
    • 2'b01: Maximum BW /2 in reconfiguration group
    • 2'b10: Maximum BW /4 in reconfiguration group
    • 2'b10: Special rate

The profile_sel signal decoding is internally based on the selected reconfiguration group:

Signal decoding for the FGT Transceivers:

  • 25GE-1 Reconfigurable Group:
    • 6'b00_00_00: 1x25GE-1/1x10GE-1 9
  • 50GE-1 Reconfigurable Group:
    • 6'b00_00_00: 1x50GE-1
    • 6'b00_00_01: 1x25GE-1/1x10GE-19
  • 100GE-4 Reconfigurable Group:
    • 6'b00_00_00: 1x100GE-4
    • 6'b00_00_11: 1x40GE-4
    • 6'b00_01_00: 1x100GE-2
    • 6'b01_00_00: 2x50GE-2
    • 6'b01_01_00: 2x50GE-1
    • 6'b10_00_00: 4x25GE-1 / 10GE-19
  • 100GE-2 Reconfigurable Group:
    • 6'b00_00_00: 1x100GE-2
    • 6'b00_00_01: 1x50GE-2
    • 6'b01_00_00: 2x50GE-1
    • 6'b01_00_01: 2x25GE-1/10GE-19
  • 400GE-8 Reconfigurable Group:
    • 6'b00_00_00: 1x400GE-8
    • 6'b01_00_00: 2x200GE-4
    • 6'b01_00_00: 4x100GE-2
  • 200GE-4 Reconfigurable Group:
    • 6'b00_00_00: 1x200GE-4
    • 6'b00_00_01: 1x100GE-4
    • 6'b01_00_00: 2x100GE-2
    • 6'b01_00_01: 2x50GE-2
    • 6'b10_00_01: 4x50GE-1
Signal decoding for the FHT transceivers:
  • 50GE-1 Reconfigurable Group:
    • 6'b00_00_00: 1x50GE-1
    • 6'b00_00_01: 1x25GE-1
  • 100GE-4 Reconfigurable Group:
    • 6'b00_00_00: 1x100GE-4
    • 6'b00_00_01: 1x100GE-2
    • 6'b00_10_00: 1x100GE-1
    • 6'b01_00_00: 2x50GE-2
    • 6'b01_01_00: 2x50GE-1
    • 6'h10_00_00: 4x50GE-1
  • 100GE-2 Reconfigurable Group:
    • 6'b00_00_00: 1x100GE-2
    • 6'b00_01_00: 1x100GE-1
    • 6'b01_00_01: 1x50GE-2
    • 6'b01_00_00: 2x50GE-1
    • 6'b01_00_010: 2x25GE-1
  • 100GE-1 Reconfigurable Group:
    • 6'b00_00_00: 1x100GE-1
    • 6'b00_00_01: 1x50GE-1
    • 6'b00_00_10: 1x25GE-1
  • 400GE-4 Reconfigurable Group:
    • 6'b00_00_00: 1x400GE-4
    • 6'b01_00_01: 1x200GE-4
    • 6'b01_00_00: 2x100GE-2
    • 6'b01_00_01: 2x100GE-2
    • 6'b10_00_00: 4x100GE-1
  • 200GE-4 Reconfigurable Group:
    • 6'b00_00_00: 1x200GE-4
    • 6'b00_01_00: 1x200GE-2
    • 6'b00_00_01: 1x100GE-4
    • 6'b01_00_00: 2x100GE-2
    • 6'b01_01_00: 2x100GE-1
    • 6'b01_00_01: 2x50GE-2
    • 6'b10_00_00: 4x50GE-1
  • 200GE-2 Reconfigurable Group:
    • 6'b00_00_00: 1x200GE-2
    • 6'b00_00_01: 1x100GE-2
    • 6'b00_00_10: 1x50GE-2
    • 6'b01_00_00: 2x100GE-1
    • 6'b01_00_00: 2x50GE-1
 Startup Profile
0x204 fec_mode[11:0] FEC Mode Register
fec_mode[11:0] = {fec_mode[11:9], fec_mode[8:6], fec_mode[5:3], fec_mode[2:0]}, where
  • fec_mode[11:9]: FEC mode for port 3
  • fec_mode[8:6]: FEC mode for port 2
  • fec_mode5:3]: FEC mode for port 1
  • fec_mode[2:0]: FEC mode for port 0
Selects the FEC type for the active ports in the selected profile:
  • 3'b000: None
  • 3'b001: IEEE 802.3 BASE-R Firecode (CL74)
  • 3'b010: IEEE 802.3 RS(528,514) (CL91)
  • 3'b011: IEEE 802.3 RS(544,514) (CL134)
  • 3'b100: Ethernet Technology Consortium RS(272, 258)
The port-specific bits only apply to the active ports in the selected profile. 		FEC mode at startup
0x208 sel_25g_10g[3:0] 10GE/25GE Selection Register: Selects the 10GE or 25GE mode for the active ports in the selected profile. The port-specific bits only apply to the active ports in the selected profile.
The bit definitions are shown below:
  • 1'b0 – 25GE is selected
  • 1'b1 – 10GE is selected

  • Bit 0 – Select 25GE/10GE for Port 0
  • Bit 1 – Select 25GE/10GE for port 1
  • Bit 2 – Select 25GE/10GE for port 2
  • Bit 3 – Select 25GE/10GE for port 3

Note that the port specific bits only apply to the active ports in the selected profile

This register is applicable only to the following profiles in FGT Reconfiguration Groups:
  • 4x 25GE/10GE profile in 100GE-4 Group
  • 2x 25GE/10GE profile in 100GE-2 Group
  • 1x 25GE/10GE profile in 25GE-1 Group
  • 1x 25GE/10GE profile in 50GE-1 Group

This register is not applicable to any FHT reconfiguration groups as FHT does not support 10GE rates.

 10GE Enable at startup
Related Information
8 This offset is only available in port 0 of the Ethernet reconfiguration Avalon® memory-mapped interface space.
9 For 10GE/25GE rate selection, use the 0x208 offset.
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