Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 4/13/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers x
7.1. Cryptographic Primary Control Register 7.2. Cryptographic Secondary Control Register 7.3. Cryptographic Primary Status Register 7.4. Cryptographic Error Status Register 7.5. Cryptographic Error Control Register 7.6. Cryptographic Packet Error Control 1 Register 7.7. Cryptographic Packet Error Control 2 Register 7.8. Cryptographic Error Code Control 1 Register 7.9. Cryptographic Error Code Control 2 Register 7.10. Cryptographic Error Code Internal Control Register 7.11. Cryptographic Internal Error Control Register 7.12. Cryptographic First Error Log Register 7.13. Cryptographic Packet Error Log 1 Register 7.14. Cryptographic Packet Error Log 2 Register 7.15. Cryptographic Internal Error Log Register 7.16. Cryptographic Wall Clock LSB Register 7.17. Cryptographic Wall Clock MSB Register 7.18. Ternary Control Register
8. Design Example x
8.1. Functional Description 8.2. Hardware and Software Requirements 8.3. Simulation Requirements 8.4. Generating the Design 8.5. Compiling the Design Example 8.6. Simulating the Design Example Testbench
8.1. Functional Description x
8.1.1. Pattern Generator and Checker
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

7.18. Ternary Control Register

Table 77.   ternary_ctrl Field Description
Offset 0x5C
Addressing Mode 32-bits
Description Ternary Control Register
Table 78.   ternary_ctrl Field Description
Bit Name Type Reset Description
31:26 ctrl RW/RO 0x0 Reserved
25 seq_sector_loopback RW/RO 0x0 Indicates sector sequential loopback
  • When set AND when secure_pio ENABLE_DFX_TEST_MODE[0] , AXI-ST CIF interface operates sequential loopback AXI-ST C2P to AXI-ST P2C after the first register boundary operating on i_cif_clk/i_sector_rstn
Requires i_cif_clk toggling and i_sector_rstn de-assert after entering user_mode
24 ext24 RW/RO 0x0 Reserved
23:16 cif_latency_pipe RW/RO 0x3C Specifies the number of clocks to delay information in the cif_datapath latency.

Must match the latency of the RMB core , minus 2 clock cycles.

15:12 ccl RW/RO 0x0 Indicates the CCL extended control:
  • [12] = 0: sideband_iv
  • [12] = 1: inband_iv
  • Others: Reserved

The first (SOB) dataword of a GCM block has the IV Static strap pin, should not be toggled while there is any data inside the EIP-338.

11:8 fiso RW/RO 0x0 Indicates memory repair FISO. You enable the signal when repair data is scanned in.
  • [8]: CIF packetizer memory
  • [9]: CIF depact memory
  • [10]: CCL memory
  • [11]: Reserved
7:4 rscen RW/RO 0x0 Indicates register scan enable input.
  • [4]: CIF packetizer memory
  • [5]: CIF depacketizer memory
  • [6]: CCL memory
  • [7]: Reserved
3:0 rscrst RW/RO 0xF Indicates memory repair RSCRST.
  • [0]: CIF packetizer memory
  • [1]: CIF depacketizer memory
  • [2]: CCL memory
  • [3]: Reserved
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