Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 4/13/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers x
7.1. Cryptographic Primary Control Register 7.2. Cryptographic Secondary Control Register 7.3. Cryptographic Primary Status Register 7.4. Cryptographic Error Status Register 7.5. Cryptographic Error Control Register 7.6. Cryptographic Packet Error Control 1 Register 7.7. Cryptographic Packet Error Control 2 Register 7.8. Cryptographic Error Code Control 1 Register 7.9. Cryptographic Error Code Control 2 Register 7.10. Cryptographic Error Code Internal Control Register 7.11. Cryptographic Internal Error Control Register 7.12. Cryptographic First Error Log Register 7.13. Cryptographic Packet Error Log 1 Register 7.14. Cryptographic Packet Error Log 2 Register 7.15. Cryptographic Internal Error Log Register 7.16. Cryptographic Wall Clock LSB Register 7.17. Cryptographic Wall Clock MSB Register 7.18. Ternary Control Register
8. Design Example x
8.1. Functional Description 8.2. Hardware and Software Requirements 8.3. Simulation Requirements 8.4. Generating the Design 8.5. Compiling the Design Example 8.6. Simulating the Design Example Testbench
8.1. Functional Description x
8.1.1. Pattern Generator and Checker
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

7.2. Cryptographic Secondary Control Register

Table 45.   ctrl_secondary Register
Offset 0x04
Addressing Mode 32-bits
Description Cryptographic secondary control register.
Table 46.   ctrl_secondary Field Description
Bit Name Type Reset Description
31:29 Reserved
29 mem_ecc_error_qual RW 0x1 ECC memory error select qualifier.

To ensure the accurate sampling of the ECC memory error status bit, the mem_ecc_error_sel control bit should only change when the mem_ecc_error_qual is not set.

27:24 mem_ecc_error_sel RW 0x7 ECC memory error selection
Selects the cryptographic memory source for the mem_ecc_derr and the mem_ecc_serr signals:
  • 4'd0: Cryptographic interface packetizer
  • 4'd1: Cryptographic interface depacketizer
  • 4'd2: Cryptographic interface MAC FIFO
  • 4'd3: Encrypto Tweak/IC RAM
  • 4'd5: Hash key powers RAM
  • 4'd6: Key1[127:64] RAM
  • 4'd7: Key1[63:0] RAM
  • 4'd8: Key2[127:64] RAM
  • 4'd9: Key2[63:0] RAM
  • 4'd10: GHash State RAM
  • 4'd11: Reserved
  • 4'd12: Proto state RAM
  • 4'd13: Key ID LUT RAM
  • 4'd14: Y0 Encrypted RAM
  • 4'd15: Reserved
23:0 Reserved RW 0x300000
Level Two Title