F-Tile SDI II FPGA IP Design Example User Guide

ID 710496
Date 10/21/2022
Public

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2.3. Functional Description

The SDI II Intel® FPGA IP core design example supports the following simplex and duplex transceiver mode:.
  • Parallel loopback with simplex mode
  • Parallel loopback with duplex mode
  • Serial loopback with simplex mode
  • Serial loopback with duplex mode
Figure 13. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = None)
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 14. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Figure 15. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = None)
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 16. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Figure 17. Serial Loopback with Simplex Mode IP Core (Enable active video data protocols = None)
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • Serial loopback design is not supported when you select AXIS-VVP Full active video data protocol.
Figure 18. Serial Loopback with Duplex Mode IP Core (Enable active video data protocols = None)
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • Serial loopback design is not supported when you select AXIS-VVP Full active video data protocol.