F-Tile SDI II FPGA IP Design Example User Guide

Download PDF
ID 710496
Date 10/21/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

2.3.2. Clocking Scheme

Figure 19. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = None)
Note: When you select None active video data protocols, the DUTs are RX top and TX top.
Figure 20. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Note: When you select AXIS-VVP Full active video data protocols, Nios® II processor drives the control and status registers ( Avalon® memory-mapped) of both the SDI II TX and RX IP cores. The available DUTs are Nios® II Subsystem, RX PHY top and TX PHY top.
Figure 21. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = None)
Note: When you select None active video data protocols, the DUT is Du top.
Figure 22. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Note:

When you select AXIS-VVP Full active video data protocols, Nios® II processor drives the control and status registers ( Avalon® memory-mapped) of both the SDI II TX and RX IP cores. The available DUTs are Nios® II Subsystem and Du PHY top.

Figure 23. Serial Loopback with Simplex Mode
Figure 24. Serial Loopback with Duplex Mode

Section Content
Clocking Scheme Component

Level Two Title