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Ixiasoft
Visible to Intel only — GUID: hco1416493261037
Ixiasoft
1.1. Memory Solutions
- Physical layer interface (PHY) which builds the data path and manages timing transfers between the FPGA and the memory device.
- Memory controller which implements all the memory commands and protocol-level requirements.
- Multi-port front end (MPFE) which allows multiple components inside the FPGA device to share a common memory interface. The MPFE is available in Intel® Arria V and Intel® Cyclone V devices.
Intel® 's FPGAs provide two types of memory solutions, depending on device family: soft memory IP and hard memory IP. The soft memory IP gives you the flexibility to design your own interfaces to meet your system requirements and still benefit from the industry leading performance. The hard memory IP is designed to give you a complete out-of-the-box experience when designing a memory controller.
The following table lists features of the soft and hard memory IP.
Soft Memory IP |
Hard Memory IP |
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Intel® provides modular memory solutions that allow you to customize your memory interface design to a variety of configurations:
- PHY with your own controller
- PHY with Intel® controller
- PHY with Intel® controller and a multiport front end. (MPFE is a configurable block available for hard interfaces in Arria V and Cyclone V devices.)
You can also build a custom PHY, a custom controller, or both, as desired.