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2.1.1. Selecting Your External Memory Device
2.1.2. Selecting Your FPGA
2.1.3. Planning Your Pin Requirements
2.1.4. Planning Your FPGA Resources
2.1.5. Determining Your Board Layout
2.1.6. Specifying Parameters for Your External Memory Interface
2.1.7. Performing Functional Simulation
2.1.8. Adding Design Constraints
2.1.9. Compiling Your Design and Verifying Timing
2.1.10. Verifying and Debugging External Memory Interface Operation
3.1. DDR SDRAM Features
3.2. DDR2 SDRAM Features
3.3. DDR3 SDRAM Features
3.4. QDR, QDR II, and QDR II+ SRAM Features
3.5. RLDRAM II and RLDRAM 3 Features
3.6. LPDDR2 Features
3.7. Memory Selection
3.8. Example of High-Speed Memory in Embedded Processor
3.9. Example of High-Speed Memory in Telecom
3.10. Document Revision History
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1.3. Arria 10 EMIF Future Protocol Support
The following table lists planned future memory protocol support for Arria 10 EMIF IP.
Protocol | Current Support | Future Support |
---|---|---|
DDR4 |
|
Yes (LRDIMM, RDIMM, x4 DQ/DQS) |
DDR3 |
|
Yes (LRDIMM, RDIMM, x4 DQ/DQS) |
DDR2 | No | Yes (via Altera PHYLite for Memory) |
LPDDR3 | Yes | Yes |
LPDDR2 | No | Yes (via Altera PHYLite for Memory) |
QDR II / II+ / QDR II+ Xtreme | Hard PHY and Soft Controller | Yes |
RLDRAM 3 | Hard PHY only | Yes |
RLDRAM II | No | Yes (via Altera PHYLite for Memory) |