F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

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ID 709308
Date 9/02/2022
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2. Parallel Loopback Design Examples

The DisplayPort Intel FPGA IP design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance without a Pixel Clock Recovery (PCR) module.
Table 4.  DisplayPort Intel FPGA IP Design Example for Intel® Agilex™ F-tile Device
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST parallel loopback without PCR DisplayPort SST RBR, HRB, HRB2, HBR3 Simplex Parallel without PCR
DisplayPort SST parallel loopback with AXIS Video Interface DisplayPort SST RBR, HRB, HRB2, HBR3 Simplex Parallel with AXIS Video Interface

Section Content
Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Features
Clocking Scheme
Simulation Testbench

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