F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

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ID 709308
Date 9/02/2022
Public

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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. Document Revision History for F-Tile DisplayPort Intel FPGA IP Design Example User Guide
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Clocking Scheme 2.3. Simulation Testbench
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. Document Revision History for F-Tile DisplayPort Intel FPGA IP Design Example User Guide

3. Document Revision History for F-Tile DisplayPort Intel FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.02 22.2 20.0.1
  • Changed document title from DisplayPort Intel Agilex F-Tile FPGA IP Design Example User Guide to F-Tile DisplayPort Intel FPGA IP Design Example User Guide.
  • Enabled AXIS Video Design Example variant.
  • Removed Static Rate design and replaced it with Multi Rate Design Example.
  • Removed the note in the DisplayPort Intel FPGA IP Design Example Quick Start Guide that says Intel Quartus Prime 21.4 software version only supports Preliminary Design Examples.
  • Replaced the Directory Structure figure with the correct figure.
  • Added a section Regenerating ELF File under Compiling and Testing the Design.
  • Updated the Hardware and Software Requirements section to include additional hardware requirements.
2021.12.13 21.4 20.0.0 Initial release.
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