Fronthaul Compression Intel® FPGA IP User Guide

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ID 709301
Date 12/07/2021
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Document Table of Contents
Document Table of Contents x
1. About the Fronthaul Compression Intel® FPGA IP 2. Getting Started with the Fronthaul Compression Intel® FPGA IP 3. Fronthaul Compression IP Functional Description 4. Fronthaul Compression IP Registers 5. Fronthaul Compression Intel FPGA IPs User Guide Archive 6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide
1. About the Fronthaul Compression Intel® FPGA IP x
1.1. Fronthaul Compression Intel® FPGA IP Features 1.2. Fronthaul Compression Intel® FPGA IP Device Family Support 1.3. Release Information for the Fronthaul Compression Intel® FPGA IP
2. Getting Started with the Fronthaul Compression Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the Fronthaul Compression IP 2.2. Parameterizing the Fronthaul Compression IP 2.3. Generated IP File Structure
2.2. Parameterizing the Fronthaul Compression IP x
2.2.1. Fronthaul Compression IP Parameters
3. Fronthaul Compression IP Functional Description x
3.1. Fronthaul Compression IP Signals
1. About the Fronthaul Compression Intel® FPGA IP
2. Getting Started with the Fronthaul Compression Intel® FPGA IP
3. Fronthaul Compression IP Functional Description
4. Fronthaul Compression IP Registers
5. Fronthaul Compression Intel FPGA IPs User Guide Archive
6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide

4. Fronthaul Compression IP Registers

Control and monitor fronthaul compression functionality through the control and status interface.
Register Map
CSR_ADDRESS (Word Offset) Register Name
0x0 compression_mode
0x1 tx_error
0x2 rx_error
compression_mode Register
Bit Width Description Access HW Reset Value
31:9 Reserved RO 0x0
8:8

Functional mode:

  • 1'b0 is static compression mode
  • 1'b1 is dynamic compression mode
 RW 0x0
7:0

Static user data compression header:

  • 7:4 is udIqWidth
    • 4’b0000 is 16 bits
    • 4’b1111 is 15 bits
    • :
    • 4’b0001 is 1 bit
  • 3:0 is udCompMeth
    • 4’b0000 is no compression
    • 4’b0001 is block floating point
    • 4’b0011 is µ-law
  • Others are reserved
RW 0x0
tx Error Register
Bit Width Description Access HW Reset Value
31:2 Reserved RO 0x0
1:1 Invalid IqWidth. The IP sets Iqwidth to 0 (16-bit Iqwidth) if it detects invalid or unsupported Iqwidth. RW1C 0x0
0:0 Invalid compression method. The IP drops the packet. RW1C 0x0
rx Error Register
Bit Width Description Access HW Reset Value
31:8 Reserved RO 0x0
1:1 Invalid IqWidth. The IP drops the packet. RW1C 0x0
0:0

Invalid compression method. The IP sets the compression method to the following default supported compression method:

  • Enabled block-floating point only: default to block-floating point.
  • Enabled μ-law only: default to μ-law.
  • Enabled both block-floating point and μ-law: default to block-floating point.
RW1C 0x0
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