4G Turbo-V Intel® FPGA IP User Guide

Download PDF
ID 683882
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Getting Started with 4G Turbo-V IP 3. Designing with the 4G Turbo-V Intel® FPGA IP 4. 4G Turbo-V Intel® FPGA IP Functional Description 5. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. 4G Turbo-V IP Release Information 1.4. 4G Turbo-V Performance and Resource Utilization
2. Getting Started with 4G Turbo-V IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 4G Turbo-V IP Timeout Behavior
3. Designing with the 4G Turbo-V Intel® FPGA IP x
3.1. Generating a 4G Turbo-V IP 3.2. Simulating the IP with the RTL Simulator 3.3. Simulating a 4G Turbo-V IP with MATLAB 3.4. Simulating a 4G Turbo-V IP with C-Models
4. 4G Turbo-V Intel® FPGA IP Functional Description x
4.1. 4G Turbo-V Downlink Accelerator 4.2. 4G Turbo-V Uplink Accelerator 4.3. 4G Turbo-V Signals and Interfaces
4.1. 4G Turbo-V Downlink Accelerator x
4.1.1. Turbo Encoder 4.1.2. Rate Matcher 4.1.3. Input and Output Data Formats 4.1.4. Latency Calculations Example 1: K = 6144, Kπ = 6176, E = 18444 Example 2: K = 40, Kπ = 64, E = 132 4.1.5. Throughput Calculations
4.2. 4G Turbo-V Uplink Accelerator x
4.2.1. Turbo Decoder 4.2.2. Input and Output Data Formats 4.2.3. Latency Calculations 4.2.4. Throughput Calculations
4.3. 4G Turbo-V Signals and Interfaces x
4.3.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Getting Started with 4G Turbo-V IP
3. Designing with the 4G Turbo-V Intel® FPGA IP
4. 4G Turbo-V Intel® FPGA IP Functional Description
5. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

4.1.4. Latency Calculations

The overall latency of the downlink accelerator is the sum of the latency of the subcomponents, CRC, encoder, subblock-interleaver, pruning, and the output latency L(output). The calculaitons do not include control and data overhead delay, which may vary from block to block. Therefore, the calculated D is the shortest processing delay.

L(crc) = K/8+8

L(encoder) = K/8+14

L(subblock-interleaver) = Kπ/8+42

L(pruning) = Kπ/8+14

L(output) = ceil(E/24)+46

Example 1: K = 6144, Kπ = 6176, E = 18444

L(crc) = 6144/8+8 = 776 cycles

L(encoder) = 6144/8+14 = 782 cycles

L(subblock-interleaver) = 6176/8+42 = 814 cycles

L(pruning) = 6176/8+14 = 786 cycles

L(output) = ceil(18444/24)+46 = 815 cycles

L(downlink) = 776 + 782 + 814 + 786 + 815 = 3973 cycles

Example 2: K = 40, Kπ = 64, E = 132

L(crc) = 40/8+8 = 13 cycles

L(encoder) = 40/8+14 = 19 cycles

L(subblock-interleaver) = 64/8+42 = 50 cycles

L(pruning) = 64/8+14 = 22 cycles

L(output) = ceil(132/24)+46 = 52 cycles

L(downlink) = 13 + 19 + 50 + 22 + 52 = 156 cycles

Level Two Title