External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

13.7.10. RLDRAM II Resource Utilization in Arria II GZ, Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices

The following table shows typical resource usage of the RLDRAM II controller with UniPHY in the current version of Quartus Prime software for Arria II GZ, Arria V GZ, Stratix III, Stratix IV, and Stratix V devices.
Table 129.  Resource Utilization in Arria II GZ, Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices   (1)

PHY Rate

Memory Width (Bits)

Combinational ALUTS

Logic Registers

Memory (Bits)

M9K Blocks

Half

9

829

763

288

1

18

1145

1147

576

2

36

1713

1861

1152

4

Full

9

892

839

288

1

18

1182

1197

576

1

36

1678

1874

1152

2

Note to Table:

  1. Half-rate designs use the same amount of memory as full-rate designs, but the data is organized in a different way (half the width, double the depth) and the design may need more M9K resources.

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