External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

12.3.4.1. Notes on Configuring UniPHY IP in Qsys

This section includes notes and tips on configuring the UniPHY IP in Qsys.
  • The address ranges shown for the Avalon-MM slave interface on the UniPHY component should be interpreted as byte addresses that an Avalon-MM master would address, despite the fact that this range is modified by configuring the word addresses width of the Avalon-MM slave interface on the UniPHY controller.
  • The afi_clk clock source is the associated clock to the Avalon-MM slave interface on the memory controller. This is the ideal clock source to use for all IP components connected on the same Avalon network. Using another clock would cause Qsys to automatically instantiate clock-crossing logic, potentially degrading performance.
  • The afi_clk clock rate is determined by the Rate on Avalon-MM interface setting on the UniPHY PHY Settings tab. The afi_half_clk clock interface has a rate which is further halved. For example, if Rate on Avalon-MM interface is set to Half, the afi_clk rate is half of the memory clock frequency, and the afi_half_clk is one quarter of the memory clock frequency.
  • The global_reset input interface can be used to reset the UniPHY memory interface and the PLL contained therein. The soft_reset input interface can be used to reset the UniPHY memory interface but allow the PLL to remain locked. You can use the soft_reset input to reset the memory but to maintain the AFI clock output to other components in the system.
  • Do not connect a reset request from a system component (such as a Nios II processor) to the UniPHY global_reset_n port. Doing so would reset the UniPHY PLL, which would propagate as a reset condition on afi_reset back to the requester; the resulting reset loop could freeze the system.
  • Qsys generates an interconnect fabric for each Avalon network. The interconnect fabric is capable of burst and width adaptation. If your UniPHY memory controller is configured with an Avalon interface data width which is wider than an Avalon-MM master interface connected to it, you must enable the byte enable signal on the Avalon-MM slave interface, by checking the Enable Avalon-MM byte-enable signal checkbox on the Controller Settings tab in the parameter editor.
  • If you have a point-to-point connection from an Avalon-MM master to the Avalon-MM slave interface on the memory controller, and if the Avalon data width and burst length settings match, then the Avalon interface data widths may be multiples of either a power of two or nine. Otherwise, you must enable Generate power-of-2 data bus widths for Qsys or SOPC Builder on the Controller Settings tab of the parameter editor.

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