External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Document Table of Contents NIOS II-based Sequencer RW Manager

The read write (RW) manager encapsulates the protocol to read and write to the memory device through the Altera PHY Interface (AFI). It provides a buffer that stores the data to be sent to and read from memory, and provides the following commands:
  • Write configuration—configures the memory for use. Sets up burst lengths, read and write latencies, and other device specific parameters.
  • Refresh—initiates a refresh operation at the DRAM. The command does not exist on SRAM devices. The sequencer also provides a register that determines whether the RW manager automatically generates refresh signals.
  • Enable or disable multi-purpose register (MPR)—for memory devices with a special register that contains calibration specific patterns that you can read, this command enables or disables access to the register.
  • Activate row—for memory devices that have both rows and columns, this command activates a specific row. Subsequent reads and writes operate on this specific row.
  • Precharge—closes a row before you can access a new row.
  • Write or read burst—writes or reads a burst length of data.
  • Write guaranteed—writes with a special mode where the memory holds address and data lines constant. Intel guarantees this type of write to work in the presence of skew, but constrains to write the same data across the entire burst length.
  • Write and read back-to-back—performs back-to-back writes or reads to adjacent banks. Most memory devices have strict timing constraints on subsequent accesses to the same bank, thus back-to-back writes and reads have to reference different banks.
  • Protocol-specific initialization—a protocol-specific command required by the initialization sequence.

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