184.108.40.206. Nios II-based Sequencer Architecture
The high-level calibration algorithms are specified in C code, which is compiled into Nios II code that resides in the FPGA RAM blocks. The debug interface provides a mechanism for interacting with the various managers and for tracking the progress of the calibration algorithm, and can be useful for debugging problems that arise within the PHY. The various managers are specified in RTL and implement operations that would be slow or inefficient if implemented in software.
The C code that defines the calibration routines is available for your reference in the \<name>_s0_software subdirectory. Intel recommends that you do not modify this C code.
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