External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Document Table of Contents

3.24. Document Revision History

Date Version Changes
May 2017 2017.05.08
  • Added Using the EMIF Debug Toolkit with Arria 10 HPS Interfaces topic.
  • Rebranded as Intel.
October 2016 2016.10.31
  • Added Back-to-Back User-Controlled Refresh for Hard Memory Controller topic.
  • Modified first bullet point in the ECC in Arria 10 EMIF IP topic.
  • Added additional content about read-modify-write operations to the ECC in Arria 10 EMIF IP topic.
  • Removed afi_alert_n from the AFI Address and Command Signals table in the AFI Address and Command Signals topic.
  • Added ecc5: Address of Most Recent SBE/DBE and ecc6: Address of Most recent Correct Command Dropped to Memory Mapped Register (MMR) Tables section.
May 2016 2016.05.02
  • Modified text of Hard Memory Controller and Hard PHY and Soft Memory Controller and Hard PHY.
  • Modified content of the Ping Pong PHY Architecture topic.
  • Added section on read-modify-write operations, to ECC in Arria 10 EMIF IP topic.
  • Added AFI 4.0 Timing Diagrams section.
  • Added Arria 10 EMIF Latency section.
  • Added Arria 10 EMIF Calibration Times section.
  • Added Integrating a Custom Controller with the Hard PHY section.
November 2015 2015.11.02
  • Added LPDDR3 support to AFI Parameters, AFI Address and Command Signals, and AFI Write Data Signals.
  • Revised rendering of address information in the Memory Mapped Register (MMR) Tables.
  • Added ecc1: ECC General Configuration, ecc2: Width Configuration, ecc3: ECC Error and Interrupt Configuration, and ecc4: Status and Error Information in the Memory Mapped Register (MMR) Tables.
  • Removed RZQ Pin Sharing section.
  • Added bank numbers to figure in Restrictions on I/O Bank Usage for Arria 10 EMIF IP with HPS topic.
  • Added Arria 10 EMIF and SmartVID topic.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04 Maintenance release.
December 2014 2014.12.15
  • Added debug-related connections to the Logical Connections table in the Logical Connections topic.
  • Added Arria 10 EMIF Ping Pong PHY section.
  • Added Arria 10 EMIF Debugging Examples section.
  • Added x4 mode support.
  • Added AFI 4.0 Specification section.
  • Added MMR Register Tables section.
August 2014 2014.08.15
  • Added PHY-only support for DDR3, DDR4, and RLDRAM 3, and soft controller and hard PHY support for RLDRAM 3 and QDR II/II+/II+ Xtreme to Supported Memory Protocols table.
  • Added afi_conduit_end, afi_clk_conduit_end, afi_half_clk_conduit_end, and afi_reset_n_conduit_end to Logical Connections table.
  • Expanded description of ctrl_amm_avalon_slave in Logical Connections table.
  • Added ECC in Arria 10 EMIF IP.
  • Added Configuring Your EMIF IP for Use with the Debug Toolkit.
  • Added Arria 10 EMIF for Hard Processor Subsystem.
December 2013 2013.12.16 Initial release.

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