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Ixiasoft
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Ixiasoft
8.2. Avalon-MM and Memory Data Width
The half-rate controller does not support burst-of-2 devices because it under-uses the available memory bandwidth. Regardless of full or half-rate decision and the device burst length, the Avalon-MM interface must supply all the data for the entire memory burst in a single clock cycle. Therefore the Avalon-MM data width of the full-rate controller with burst-of-4 devices is four times the memory data width. For width-expanded configurations, the data width is further multiplied by the expansion factor (not shown in table 5-1 and 5-2).
Memory Burst Length |
Half-Rate Designs |
Full-Rate Designs |
---|---|---|
QDR II 2-word burst |
No Support |
2:1 |
QDR II, QDR II+, and QDR II+ Extreme 4-word burst |
4:1 |