Intel Agilex® 7 Device Security User Guide

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ID 683823
Date 7/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Device Security Overview 2. Authentication and Authorization 3. AES Bitstream Encryption 4. Device Provisioning 5. Advanced Features 6. Troubleshooting 7. Intel Agilex® 7 Device Security User Guide Archives 8. Revision History for the Intel Agilex® 7 Device Security User Guide
1. Intel Agilex® 7 Device Security Overview x
1.1. Commitment to Product Security 1.2. Available Security Documentation
2. Authentication and Authorization x
2.1. Creating a Signature Chain 2.2. Signing a Configuration Bitstream
2.1. Creating a Signature Chain x
2.1.1. Creating Authentication Key Pairs on the Local File System 2.1.2. Creating Authentication Key Pairs in SoftHSM 2.1.3. Creating the Signature Chain Root Entry 2.1.4. Creating a Signature Chain Public Key Entry
2.2. Signing a Configuration Bitstream x
2.2.1. Quartus Key File Assignment 2.2.2. Co-Signing SDM Firmware 2.2.3. Signing Configuration Bitstream Using the quartus_sign Command 2.2.4. Partial Reconfiguration Multi-Authority Support 2.2.5. Verifying Configuration Bitstream Signature Chains
3. AES Bitstream Encryption x
3.1. Creating the AES Root Key 3.2. Quartus Encryption Settings 3.3. Encrypting a Configuration Bitstream
3.3. Encrypting a Configuration Bitstream x
3.3.1. Configuration Bitstream Encryption Using the Programming File Generator Graphical Interface 3.3.2. Configuration Bitstream Encryption Using the Programming File Generator Command Line Interface 3.3.3. Partially Encrypted Configuration Bitstream Generation Using the Command Line Interface 3.3.4. Partial Reconfiguration Bitstream Encryption
4. Device Provisioning x
4.1. Using SDM Provision Firmware 4.2. Using QSPI Factory Default Helper Image on Owned Devices 4.3. Authentication Root Key Provisioning 4.4. Programming Key Cancellation ID Fuses 4.5. Canceling Root Keys 4.6. Programming Counter Fuses 4.7. Secure Data Object Service Root Key Provisioning 4.8. Security Setting Fuse Provisioning 4.9. AES Root Key Provisioning 4.10. Converting Owner Root Key, AES Root Key Certificates, and Fuse files to Jam STAPL File Formats
4.3. Authentication Root Key Provisioning x
4.3.1. Partial Reconfiguration Multi-Authority Root Key Programming
4.9. AES Root Key Provisioning x
4.9.1. AES Root Key Compact Certificate 4.9.2. Intrinsic ID® PUF AES Root Key Provisioning 4.9.3. Black Key Provisioning
4.9.2. Intrinsic ID® PUF AES Root Key Provisioning x
4.9.2.1. Intrinsic ID PUF Enrollment 4.9.2.2. Wrapping the AES Root Key 4.9.2.3. Programming Helper Data and Wrapped Key to QSPI Flash Memory 4.9.2.4. Querying Intrinsic ID PUF Activation Status 4.9.2.5. Location of the PUF in Flash Memory
4.9.3. Black Key Provisioning x
4.9.3.1. Black Key Provisioning Options
5. Advanced Features x
5.1. Secure Debug Authorization 5.2. HPS Debug Certificates 5.3. Platform Attestation 5.4. Physical Anti-Tamper 5.5. Using Design Security Features with Remote System Update 5.6. SDM Cryptographic Services 5.7. Bitstream Security Settings
5.4. Physical Anti-Tamper x
5.4.1. Anti-Tamper Responses 5.4.2. Anti-Tamper Detection 5.4.3. Anti-Tamper Lite Intel® FPGA IP
5.4.3. Anti-Tamper Lite Intel® FPGA IP x
5.4.3.1. Release Information
5.6. SDM Cryptographic Services x
5.6.1. Vendor Authorized Boot 5.6.2. Secure Data Object Service 5.6.3. SDM Cryptographic Primitive Services
5.7. Bitstream Security Settings x
5.7.1. Selecting and Enabling Security Options
6. Troubleshooting x
6.1. Using Quartus Commands in a Windows Environment Error 6.2. Generating a Private Key Warning 6.3. Adding a Signing Key to the Quartus Project Error 6.4. Generating Quartus Prime Programming File was Unsuccessful 6.5. Unknown Argument Errors 6.6. Bitstream Encryption Option Disabled Error 6.7. Specifying Correct Path to the Key 6.8. Using Unsupported Output File Type
1. Intel Agilex® 7 Device Security Overview
2. Authentication and Authorization
3. AES Bitstream Encryption
4. Device Provisioning
5. Advanced Features
6. Troubleshooting
7. Intel Agilex® 7 Device Security User Guide Archives
8. Revision History for the Intel Agilex® 7 Device Security User Guide

5.6. SDM Cryptographic Services

The SDM on Intel Agilex® 7 devices provides cryptographic services that FPGA fabric logic or the HPS may request via the respective SDM mailbox interface. For more information about the mailbox commands and data formats for all SDM cryptographic services, refer to Appendix B in the Security Methodology for Intel FPGAs and Structured ASICs User Guide.

To access the SDM mailbox interface to FPGA fabric logic for SDM cryptographic services, you must instantiate the Mailbox Client Intel FPGA IP in your design.

Reference code to access to the SDM mailbox interface from the HPS is included in the ATF and Linux code provided by Intel.


Section Content
Vendor Authorized Boot
Secure Data Object Service
SDM Cryptographic Primitive Services

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