Intel Agilex® 7 Device Security User Guide

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ID 683823
Date 7/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Device Security Overview 2. Authentication and Authorization 3. AES Bitstream Encryption 4. Device Provisioning 5. Advanced Features 6. Troubleshooting 7. Intel Agilex® 7 Device Security User Guide Archives 8. Revision History for the Intel Agilex® 7 Device Security User Guide
1. Intel Agilex® 7 Device Security Overview x
1.1. Commitment to Product Security 1.2. Available Security Documentation
2. Authentication and Authorization x
2.1. Creating a Signature Chain 2.2. Signing a Configuration Bitstream
2.1. Creating a Signature Chain x
2.1.1. Creating Authentication Key Pairs on the Local File System 2.1.2. Creating Authentication Key Pairs in SoftHSM 2.1.3. Creating the Signature Chain Root Entry 2.1.4. Creating a Signature Chain Public Key Entry
2.2. Signing a Configuration Bitstream x
2.2.1. Quartus Key File Assignment 2.2.2. Co-Signing SDM Firmware 2.2.3. Signing Configuration Bitstream Using the quartus_sign Command 2.2.4. Partial Reconfiguration Multi-Authority Support 2.2.5. Verifying Configuration Bitstream Signature Chains
3. AES Bitstream Encryption x
3.1. Creating the AES Root Key 3.2. Quartus Encryption Settings 3.3. Encrypting a Configuration Bitstream
3.3. Encrypting a Configuration Bitstream x
3.3.1. Configuration Bitstream Encryption Using the Programming File Generator Graphical Interface 3.3.2. Configuration Bitstream Encryption Using the Programming File Generator Command Line Interface 3.3.3. Partially Encrypted Configuration Bitstream Generation Using the Command Line Interface 3.3.4. Partial Reconfiguration Bitstream Encryption
4. Device Provisioning x
4.1. Using SDM Provision Firmware 4.2. Using QSPI Factory Default Helper Image on Owned Devices 4.3. Authentication Root Key Provisioning 4.4. Programming Key Cancellation ID Fuses 4.5. Canceling Root Keys 4.6. Programming Counter Fuses 4.7. Secure Data Object Service Root Key Provisioning 4.8. Security Setting Fuse Provisioning 4.9. AES Root Key Provisioning 4.10. Converting Owner Root Key, AES Root Key Certificates, and Fuse files to Jam STAPL File Formats
4.3. Authentication Root Key Provisioning x
4.3.1. Partial Reconfiguration Multi-Authority Root Key Programming
4.9. AES Root Key Provisioning x
4.9.1. AES Root Key Compact Certificate 4.9.2. Intrinsic ID® PUF AES Root Key Provisioning 4.9.3. Black Key Provisioning
4.9.2. Intrinsic ID® PUF AES Root Key Provisioning x
4.9.2.1. Intrinsic ID PUF Enrollment 4.9.2.2. Wrapping the AES Root Key 4.9.2.3. Programming Helper Data and Wrapped Key to QSPI Flash Memory 4.9.2.4. Querying Intrinsic ID PUF Activation Status 4.9.2.5. Location of the PUF in Flash Memory
4.9.3. Black Key Provisioning x
4.9.3.1. Black Key Provisioning Options
5. Advanced Features x
5.1. Secure Debug Authorization 5.2. HPS Debug Certificates 5.3. Platform Attestation 5.4. Physical Anti-Tamper 5.5. Using Design Security Features with Remote System Update 5.6. SDM Cryptographic Services 5.7. Bitstream Security Settings
5.4. Physical Anti-Tamper x
5.4.1. Anti-Tamper Responses 5.4.2. Anti-Tamper Detection 5.4.3. Anti-Tamper Lite Intel® FPGA IP
5.4.3. Anti-Tamper Lite Intel® FPGA IP x
5.4.3.1. Release Information
5.6. SDM Cryptographic Services x
5.6.1. Vendor Authorized Boot 5.6.2. Secure Data Object Service 5.6.3. SDM Cryptographic Primitive Services
5.7. Bitstream Security Settings x
5.7.1. Selecting and Enabling Security Options
6. Troubleshooting x
6.1. Using Quartus Commands in a Windows Environment Error 6.2. Generating a Private Key Warning 6.3. Adding a Signing Key to the Quartus Project Error 6.4. Generating Quartus Prime Programming File was Unsuccessful 6.5. Unknown Argument Errors 6.6. Bitstream Encryption Option Disabled Error 6.7. Specifying Correct Path to the Key 6.8. Using Unsupported Output File Type
1. Intel Agilex® 7 Device Security Overview
2. Authentication and Authorization
3. AES Bitstream Encryption
4. Device Provisioning
5. Advanced Features
6. Troubleshooting
7. Intel Agilex® 7 Device Security User Guide Archives
8. Revision History for the Intel Agilex® 7 Device Security User Guide

5.4.2. Anti-Tamper Detection

You may individually enable the frequency, temperature, and voltage detection features of the SDM. FPGA detection depends on including the Anti-Tamper Lite Intel® FPGA IP in your design.
Note: SDM frequency and voltage tamper detection methods are dependent on internal references and measurement hardware that can vary across devices. Intel recommends that you characterize the behavior of tamper detection settings.

Frequency tamper detection operates on the configuration clock source. To enable frequency tamper detection, you must specify an option other than Internal Oscillator in the Configuration clock source dropdown on the Assignments > Device > Device and Pin Options > General tab. You must ensure that the Run configuration CPU from internal oscillator checkbox is enabled prior to enabling the frequency tamper detection.

Figure 17. Setting the SDM to Internal Oscillator

To enable frequency tamper detection, select the Enable frequency tamper detection checkbox and select the desired Frequency tamper detection range from the dropdown menu.

Figure 18. Enabling Frequency Tamper Detection
Alternatively, you may enable Frequency Tamper Detection by making the following changes to the Quartus Prime Settings .qsf file: 
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ
set_global_assignment -name RUN_CONFIG_CPU_FROM_INT_OSC ON
set_global_assignment -name ENABLE_FREQUENCY_TAMPER_DETECTION ON
set_global_assignment -name FREQUENCY_TAMPER_DETECTION_RANGE 35

To enable temperature tamper detection, select the Enable temperature tamper detection checkbox and select the desired temperature upper and lower bounds in the corresponding fields. The upper and lower bounds are populated by default with the related temperature range for the device selected in the design.

To enable voltage tamper detection, you select either or both of the Enable VCCL voltage tamper detection or Enable VCCL_SDM voltage tamper detection checkboxes and select the desired Voltage tamper detection trigger percentage in the corresponding field.

Figure 19. Enabling Voltage Tamper Detection

Alternatively, you may enable Voltage Tamper Detection by specifying the following assignments in the .qsf file: 

set_global_assignment -name ENABLE_TEMPERATURE_TAMPER_DETECTION ON
set_global_assignment -name TEMPERATURE_TAMPER_UPPER_BOUND 100
set_global_assignment -name ENABLE_VCCL_VOLTAGE_TAMPER_DETECTION ON
set_global_assignment -name ENABLE_VCCL_SDM_VOLTAGE_TAMPER_DETECTION ON
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