Intel® Agilex™ Device Security User Guide

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ID 683823
Date 11/22/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Agilex® Device Security Overview 2. Authentication and Authorization 3. AES Bitstream Encryption 4. Device Provisioning 5. Advanced Features 6. Intel® Agilex™ Device Security User Guide Archives 7. Revision History for the Intel® Agilex® Device Security User Guide
1. Intel® Agilex® Device Security Overview x
1.1. Commitment to Product Security 1.2. Planned Security Features 1.3. Available Security Documentation
1.2. Planned Security Features x
1.2.1. Partial Reconfiguration Bitstream Security Verification 1.2.2. Device Self-Kill for Physical Anti-Tamper
2. Authentication and Authorization x
2.1. Creating a Signature Chain 2.2. Signing a Configuration Bitstream
2.1. Creating a Signature Chain x
2.1.1. Creating Authentication Key Pairs on the Local File System 2.1.2. Creating Authentication Key Pairs in SoftHSM 2.1.3. Creating the Signature Chain Root Entry 2.1.4. Creating a Signature Chain Public Key Entry
2.2. Signing a Configuration Bitstream x
2.2.1. Quartus Key File Assignment 2.2.2. Co-Signing SDM Firmware 2.2.3. Signing Configuration Bitstream Using the quartus_sign Command 2.2.4. Partial Reconfiguration Multi-Authority Support 2.2.5. Verifying Configuration Bitstream Signature Chains
3. AES Bitstream Encryption x
3.1. Creating the AES Root Key 3.2. Quartus Encryption Settings 3.3. Encrypting a Configuration Bitstream
3.3. Encrypting a Configuration Bitstream x
3.3.1. Configuration Bitstream Encryption Using the Programming File Generator Graphical Interface 3.3.2. Configuration Bitstream Encryption Using the Programming File Generator Command Line Interface 3.3.3. Partially Encrypted Configuration Bitstream Generation Using the Command Line Interface 3.3.4. Partial Reconfiguration Bitstream Encryption
4. Device Provisioning x
4.1. Using SDM Provision Firmware 4.2. Using QSPI Factory Default Helper Image on Owned Devices 4.3. Authentication Root Key Provisioning 4.4. Programming Key Cancellation ID Fuses 4.5. Canceling Root Keys 4.6. Programming Counter Fuses 4.7. Secure Data Object Service Root Key Provisioning 4.8. Security Setting Fuse Provisioning 4.9. AES Root Key Provisioning 4.10. Converting Owner Root Key, AES Root Key Certificates, and Fuse files to Jam STAPL File Formats
4.3. Authentication Root Key Provisioning x
4.3.1. Partial Reconfiguration Multi-Authority Root Key Programming
4.9. AES Root Key Provisioning x
4.9.1. AES Root Key Compact Certificate 4.9.2. Intrinsic ID® PUF AES Root Key Provisioning 4.9.3. Black Key Provisioning
4.9.2. Intrinsic ID® PUF AES Root Key Provisioning x
4.9.2.1. Intrinsic ID PUF Enrollment 4.9.2.2. Wrapping the AES Root Key 4.9.2.3. Programming Helper Data and Wrapped Key to QSPI Flash Memory 4.9.2.4. Querying Intrinsic ID PUF Activation Status 4.9.2.5. Location of the PUF in Flash Memory
4.9.3. Black Key Provisioning x
4.9.3.1. Black Key Provisioning Options
5. Advanced Features x
5.1. Secure Debug Authorization 5.2. HPS Debug Certificates 5.3. Platform Attestation 5.4. Physical Anti-Tamper 5.5. Using Design Security Features with Remote System Update 5.6. SDM Cryptographic Services
5.4. Physical Anti-Tamper x
5.4.1. Anti-Tamper Responses 5.4.2. Anti-Tamper Detection 5.4.3. Anti-Tamper Lite Intel® FPGA IP
5.4.3. Anti-Tamper Lite Intel® FPGA IP x
5.4.3.1. Release Information
5.6. SDM Cryptographic Services x
5.6.1. Vendor Authorized Boot 5.6.2. Secure Data Object Service 5.6.3. SDM Cryptographic Primitive Services
1. Intel® Agilex® Device Security Overview
2. Authentication and Authorization
3. AES Bitstream Encryption
4. Device Provisioning
5. Advanced Features
6. Intel® Agilex™ Device Security User Guide Archives
7. Revision History for the Intel® Agilex® Device Security User Guide

4.9.2.5. Location of the PUF in Flash Memory

The location of the PUF file is different for designs that support RSU and designs that do not support the RSU feature.

For designs that do not support RSU, you must include the .puf and .wkey files when you create updated flash images. For designs that support RSU, the SDM does not overwrite the PUF data sections during factory or application image updates.

Table 2.  Flash Sub-Partitions Layout without RSU Support
Flash Offset Size (in bytes) Contents Description
0 K 256 K Configuration Management Firmware Firmware that runs on SDM.
256 K 256 K Configuration Management Firmware
512 K 256 K Configuration Management Firmware
768 K 256 K Configuration Management Firmware
1M 32 K PUF data copy 0 Data structure for storing PUF helper data and PUF-wrapped AES root key copy 0
1M+32 K 32 K PUF data copy 1 Data structure for storing PUF helper data and PUF-wrapped AES root key copy 1
Table 3.  Flash Sub-Partitions Layout with RSU Support
Flash Offset Size (in bytes) Contents Description
0 K 512 K Decision firmware Firmware to identify and load the highest priority image.
512 K 512 K Decision firmware
1 M 512 K Decision firmware
1.5 M 512 K Decision firmware
2 M 8 K + 24K Padding Decision firmware data Reserved for Decision firmware use.
2 M + 32 K 32 K Reserved for SDM Reserved for SDM.
2 M + 64 K Variable Factory image A simple image that you create as a backup if all other application images fail to load. This image includes the CMF that runs on the SDM.
Next 32 K PUF data copy 0 Data structure for storing PUF helper data and PUF-wrapped AES root key copy 0
Next +32 K 32 K PUF data copy 1 Data structure for storing PUF helper data and PUF-wrapped AES root key copy 1
Next + 256 K 4 K Sub-partition table copy 0 Data structure to facilitate the management of the flash storage.
Next +32 K 4 K Sub-partition table copy 1
Next +32 K 4 K CMF pointer block copy 0 A list of pointers to application images in order of priority. When you add an image, that image becomes the highest.
Next +32 K   CMF pointer block copy 1 A second copy of the list of pointers to application images.
Variable Variable Application image 1 Your first application image.
Variable Variable Application image 2 Your second application image.
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