Visible to Intel only — GUID: htm1718317596284
Ixiasoft
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.2.0] [P-Tile: 8.2.0] [F-Tile: 9.2.0] [R-Tile: 5.2.0]
1.2. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0]
1.3. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.1.0] [P-Tile: 7.1.0] [F-Tile: 8.0.0] [R-Tile: 4.1.0]
1.4. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.0.0] [P-Tile: 7.0.0] [F-Tile: 7.0.0] [R-Tile: 4.0.0]
1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.3.0] [P-Tile: 6.0.0] [F-Tile: 6.0.0] [R-Tile: 3.0.0]
1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.2.0] [P-Tile: 5.1.0] [F-Tile: 5.1.0] [R-Tile: 2.0.0]
1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0]
1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.0.0] [P-Tile: 4.0.0] [F-Tile: 4.0.0]
1.9. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.5.0 ] [P-Tile: 3.1.0 ] [F-Tile: 3.0.0 ]
1.10. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.4.0 ] [P-Tile: 3.0.0] [F-Tile: 2.0.0]
1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.3.0] [P-Tile: 2.2.0] [F-Tile: 1.1.0]
1.12. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.2.0] [P-Tile: 2.1.0] [F-Tile: 1.0.0]
1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0]
1.14. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0]
1.15. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core v20.0.0
1.16. Multi Channel DMA Intel FPGA IP for PCI Express : User Guide Archives
Visible to Intel only — GUID: htm1718317596284
Ixiasoft
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0]
Quartus® Prime Version | IP Version | Description | Impact |
---|---|---|---|
24.2 | [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0] |
Added support for the MCDMA PIO interface 32-bit access capability for the R-Tile and F-Tile MCDMA IPs for Agilex™ 7 I-Series devices. | You can implement the 32-bit PIO interface access in your IP. |
Updated the Questasim* simulation command in the User Guide. | Fixed the Questasim* simulation command in the User Guide, For additional details, refer to the Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide. | ||
Added support for Agilex™ 9 devices in F-Tile. | The F-Tile Multi Channel DMA IP supports the Agilex™ 9 device family with Simulation, Compilation, and Timing (SCT) support. |