Multi Channel DMA Intel® FPGA IP for PCI Express* Release Notes

ID 683791
Date 11/04/2024
Public
Document Table of Contents

1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0]

Table 1.  Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0] : 2024.07.08
Quartus® Prime Version IP Version Description Impact
24.2

[H-Tile: 24.1.0]

[P-Tile: 8.1.0]

[F-Tile: 9.1.0]

[R-Tile: 5.1.0]

Added support for the MCDMA PIO interface 32-bit access capability for the R-Tile and F-Tile MCDMA IPs for Agilex™ 7 I-Series devices. You can implement the 32-bit PIO interface access in your IP.
Updated the Questasim* simulation command in the User Guide. Fixed the Questasim* simulation command in the User Guide, For additional details, refer to the Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide.
Added support for Agilex™ 9 devices in F-Tile. The F-Tile Multi Channel DMA IP supports the Agilex™ 9 device family with Simulation, Compilation, and Timing (SCT) support.