Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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8.2.9.4. SDRAM L3 Interconnect Resets

The reset signal l3_rst_n resets the system interconnect and the SDRAM L3 interconnect, but not the hard memory controller.

The reset signal in the hard memory controller is automatically connected to the SDRAM L3 interconnect when you instantiate the HPS component. For information about resetting the hard memory controller, refer to the External Memory Interfaces in Arria 10 Devices chapter of the Arria 10 Core Fabric and General Purpose I/O Handbook.

Soft logic in the FPGA must support the global_reset_n signal correctly. Refer to the Instantiating the HPS Component chapter for information about global_reset_n.

To optionally preserve the contents of the SDRAM on reset, refer to "Reset Handshaking" in the Reset Manager chapter.

Figure 37. Recommended SDRAM Reset Connections
Note: It is important to connect the reset user logic directly to both the HPS and the hard memory controller. If the hard memory controller is reset while the HPS is still running, the HPS is unable to access any external SDRAM memory.