Intel® Stratix® 10 Device Security User Guide

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ID 683642
Date 7/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Stratix 10 Device Security Overview 2. Authentication and Authorization 3. AES Bitstream Encryption 4. Device Provisioning 5. Advanced Features 6. Troubleshooting 7. Intel® Stratix® 10 Device Security User Guide Archives 8. Document Revision History for Intel® Stratix® 10 Device Security User Guide
1. Intel Stratix 10 Device Security Overview x
1.1. Commitment to Product Security
2. Authentication and Authorization x
2.1. Creating a Signature Chain 2.2. Signing a Configuration Bitstream
2.1. Creating a Signature Chain x
2.1.1. Creating Authentication Key Pairs on the Local File System 2.1.2. Creating Authentication Key Pairs in SoftHSM 2.1.3. Creating the Signature Chain Root Entry 2.1.4. Creating a Signature Chain Public Key Entry
2.2. Signing a Configuration Bitstream x
2.2.1. Quartus Key File Assignment 2.2.2. Co-Signing SDM Firmware 2.2.3. Signing Configuration Bitstream Using the quartus_sign Command 2.2.4. Verifying Configuration Bitstream Signature Chains
3. AES Bitstream Encryption x
3.1. Creating the AES Root Key 3.2. Quartus Encryption Settings 3.3. Encrypting a Configuration Bitstream
3.3. Encrypting a Configuration Bitstream x
3.3.1. Configuration Bitstream Encryption Using the Programming File Generator Graphical Interface 3.3.2. Configuration Bitstream Encryption Using the Programming File Generator Command Line Interface 3.3.3. Partially Encrypted Configuration Bitstream Generation Using the Command Line Interface 3.3.4. Partial Reconfiguration Bitstream Encryption
4. Device Provisioning x
4.1. Using SDM Provision Firmware 4.2. Authentication Root Key Provisioning 4.3. Using QSPI Factory Default Helper Image on Owned Devices 4.4. Programming Key Cancellation ID Fuses 4.5. Security Setting Fuse Provisioning 4.6. AES Root Key Provisioning 4.7. Converting Owner Root Key, AES Root Key Certificates, and Fuse files to Jam STAPL File Formats
4.6. AES Root Key Provisioning x
4.6.1. AES Root Key Compact Certificate 4.6.2. Intrinsic ID® PUF AES Root Key Provisioning 4.6.3. Black Key Provisioning
4.6.2. Intrinsic ID® PUF AES Root Key Provisioning x
4.6.2.1. Intrinsic ID PUF Enrollment 4.6.2.2. Wrapping the AES Root Key 4.6.2.3. Programming Helper Data and Wrapped Key to QSPI Flash Memory 4.6.2.4. Querying Intrinsic ID PUF Activation Status 4.6.2.5. Location of the PUF in Flash Memory
4.6.3. Black Key Provisioning x
4.6.3.1. Black Key Provisioning Options
5. Advanced Features x
5.1. Secure Debug Authorization 5.2. HPS Debug Certificates 5.3. Platform Attestation 5.4. Physical Anti-Tamper 5.5. Using Design Security Features with Remote System Update 5.6. Bitstream Security Settings
5.4. Physical Anti-Tamper x
5.4.1. Anti-Tamper Responses 5.4.2. Anti-Tamper Detection 5.4.3. Anti-Tamper Lite Intel® FPGA IP
5.4.3. Anti-Tamper Lite Intel® FPGA IP x
5.4.3.1. Release Information
5.6. Bitstream Security Settings x
5.6.1. Selecting and Enabling Security Options
6. Troubleshooting x
6.1. Using Quartus Commands in a Windows Environment Error 6.2. Generating a Private Key Warning 6.3. Adding a Signing Key to the Quartus Project Error 6.4. Generating Quartus Prime Programming File was Unsuccessful 6.5. Unknown Argument Errors 6.6. Bitstream Encryption Option Disabled Error 6.7. Specifying Correct Path to the Key 6.8. Using Unsupported Output File Type
1. Intel Stratix 10 Device Security Overview
2. Authentication and Authorization
3. AES Bitstream Encryption
4. Device Provisioning
5. Advanced Features
6. Troubleshooting
7. Intel® Stratix® 10 Device Security User Guide Archives
8. Document Revision History for Intel® Stratix® 10 Device Security User Guide

3.3.4. Partial Reconfiguration Bitstream Encryption

You can enable bitstream encryption on some Intel Stratix 10 FPGA designs that use partial reconfiguration.

Partial reconfiguration designs utilizing the Hierarchical Partial Reconfiguration (HPR), or Static Update Partial Reconfiguration (SUPR) do not support the bitstream encryption. You must use the same encryption key to encrypt the static region and all personas unless multi-authority support is enabled. If your design contains multiple PR regions, you must encrypt all personas.

To enable partial reconfiguration bitstream encryption, follow the same procedure in all design revisions.

  1. On the Intel® Quartus® Prime File menu, select Assignments > Device > Device and Pin Options > Security.
  2. Select the desired encryption key storage location.
    Figure 5. Partial Reconfiguration Bitstream Encryption Setting

    Alternatively, you may add the following assignment statement in the Quartus Prime settings file .qsf: 

    set_global_assignment -name \
--ENABLE_PARTIAL_RECONFIGURATION_BITSTREAM_ENCRYPTION on

    After you compile your base design and revisions, the software generates a .sof file and one or more .pmsf files, representing the personas.

  3. Create encrypted and signed programming files from .sof  and .pmsf  files in a similar fashion to designs with no partial reconfiguration enabled.
  4. Convert the compiled persona .pmsf file to a partially encrypted .rbf file: 
    quartus_pfg -c -o finalize_encryption_later=ON \ 
-o sign_later=ON encryption_enabled_persona1.pmsf persona1.rbf
  5. Finalize bitstream encryption using the quartus_encrypt command line tool: 
    quartus_encrypt --family=stratix10 \  
--operation=ENCRYPT --key=aes_root.qek persona1.rbf encrypted_persona1.rbf
  6. Sign the encrypted configuration bitstream using the quartus_sign command line tool: 
    quartus_sign --family=stratix10 --operation=SIGN \ 
--qky=design0_sign_chain.qky \ 
--pem=design0_sign_private.pem encrypted_persona1.rbf \ signed_encrypted_persona1.rbf 
    quartus_sign --family=stratix10 --operation=SIGN \ 
--module=softHSM --module_args="--token_label=s10-token \
--user_pin=s10-token-pin --hsm_lib=/usr/local/lib/softhsm/libsofthsm2.so" \
--qky=design0_sign_chain.qky --keyname=design0_sign encrypted_persona1.rbf \
signed_encrypted_persona1.rbf
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