Intel® Stratix® 10 Device Security User Guide

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ID 683642
Date 7/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Stratix 10 Device Security Overview 2. Authentication and Authorization 3. AES Bitstream Encryption 4. Device Provisioning 5. Advanced Features 6. Troubleshooting 7. Intel® Stratix® 10 Device Security User Guide Archives 8. Document Revision History for Intel® Stratix® 10 Device Security User Guide
1. Intel Stratix 10 Device Security Overview x
1.1. Commitment to Product Security
2. Authentication and Authorization x
2.1. Creating a Signature Chain 2.2. Signing a Configuration Bitstream
2.1. Creating a Signature Chain x
2.1.1. Creating Authentication Key Pairs on the Local File System 2.1.2. Creating Authentication Key Pairs in SoftHSM 2.1.3. Creating the Signature Chain Root Entry 2.1.4. Creating a Signature Chain Public Key Entry
2.2. Signing a Configuration Bitstream x
2.2.1. Quartus Key File Assignment 2.2.2. Co-Signing SDM Firmware 2.2.3. Signing Configuration Bitstream Using the quartus_sign Command 2.2.4. Verifying Configuration Bitstream Signature Chains
3. AES Bitstream Encryption x
3.1. Creating the AES Root Key 3.2. Quartus Encryption Settings 3.3. Encrypting a Configuration Bitstream
3.3. Encrypting a Configuration Bitstream x
3.3.1. Configuration Bitstream Encryption Using the Programming File Generator Graphical Interface 3.3.2. Configuration Bitstream Encryption Using the Programming File Generator Command Line Interface 3.3.3. Partially Encrypted Configuration Bitstream Generation Using the Command Line Interface 3.3.4. Partial Reconfiguration Bitstream Encryption
4. Device Provisioning x
4.1. Using SDM Provision Firmware 4.2. Authentication Root Key Provisioning 4.3. Using QSPI Factory Default Helper Image on Owned Devices 4.4. Programming Key Cancellation ID Fuses 4.5. Security Setting Fuse Provisioning 4.6. AES Root Key Provisioning 4.7. Converting Owner Root Key, AES Root Key Certificates, and Fuse files to Jam STAPL File Formats
4.6. AES Root Key Provisioning x
4.6.1. AES Root Key Compact Certificate 4.6.2. Intrinsic ID® PUF AES Root Key Provisioning 4.6.3. Black Key Provisioning
4.6.2. Intrinsic ID® PUF AES Root Key Provisioning x
4.6.2.1. Intrinsic ID PUF Enrollment 4.6.2.2. Wrapping the AES Root Key 4.6.2.3. Programming Helper Data and Wrapped Key to QSPI Flash Memory 4.6.2.4. Querying Intrinsic ID PUF Activation Status 4.6.2.5. Location of the PUF in Flash Memory
4.6.3. Black Key Provisioning x
4.6.3.1. Black Key Provisioning Options
5. Advanced Features x
5.1. Secure Debug Authorization 5.2. HPS Debug Certificates 5.3. Platform Attestation 5.4. Physical Anti-Tamper 5.5. Using Design Security Features with Remote System Update 5.6. Bitstream Security Settings
5.4. Physical Anti-Tamper x
5.4.1. Anti-Tamper Responses 5.4.2. Anti-Tamper Detection 5.4.3. Anti-Tamper Lite Intel® FPGA IP
5.4.3. Anti-Tamper Lite Intel® FPGA IP x
5.4.3.1. Release Information
5.6. Bitstream Security Settings x
5.6.1. Selecting and Enabling Security Options
6. Troubleshooting x
6.1. Using Quartus Commands in a Windows Environment Error 6.2. Generating a Private Key Warning 6.3. Adding a Signing Key to the Quartus Project Error 6.4. Generating Quartus Prime Programming File was Unsuccessful 6.5. Unknown Argument Errors 6.6. Bitstream Encryption Option Disabled Error 6.7. Specifying Correct Path to the Key 6.8. Using Unsupported Output File Type
1. Intel Stratix 10 Device Security Overview
2. Authentication and Authorization
3. AES Bitstream Encryption
4. Device Provisioning
5. Advanced Features
6. Troubleshooting
7. Intel® Stratix® 10 Device Security User Guide Archives
8. Document Revision History for Intel® Stratix® 10 Device Security User Guide

1. Intel Stratix 10 Device Security Overview

Updated for:
Intel® Quartus® Prime Design Suite 23.1

Intel® designs the Intel Stratix 10 devices with dedicated, highly-configurable security hardware and firmware.

This document contains instructions to help you use Intel® Quartus® Prime Pro Edition software to implement security features on your Intel Stratix 10 devices.

Additionally, the Security Methodology for Intel FPGAs and Structured ASICs User Guide is available on the Intel® Resource & Design Center. This document contains detailed descriptions of the security features and technologies that are available through Intel Programmable Solutions products to help you select the security features necessary to meet your security objectives. Contact Intel Support with reference number 14014613136 to access the Security Methodology for Intel FPGAs and Structured ASICs User Guide.

The document is organized as follows:

  • Authentication and Authorization: Provides instructions to create authentication keys and signature chains, apply permissions and cancellation IDs, sign objects, and program authentication features on Intel Stratix 10 devices.

  • AES Bitstream Encryption: Provides instructions to create an AES root key, encrypt configuration bitstreams, and provision the AES root key to Intel Stratix 10 devices.

  • Device Provisioning: Provides instructions to use the Intel® Quartus® Prime Programmer and Secure Device Manager (SDM) provision firmware to program security features on Intel Stratix 10 devices.

  • Advanced Features: Provides instructions to enable advanced security features, including secure debug authorization, Hard Processor System (HPS) debug, platform attestation, physical anti-tamper, and remote system update.

The following table lists the security features for specified Intel® Stratix® 10 devices.

Table 1.   Intel® Stratix® 10 Device Support for Security Features Intel recommends using only devices with a -BK ordering part number (OPN) suffix for use with the black key provisioning feature.
Intel® Stratix® 10 Device Authentication Advanced Security Black Key Provisioning
GX Yes -AS suffix devices -BK suffix devices
GX 10M Yes No -BK suffix devices
SX Yes -AS suffix devices -BK suffix devices
MX Yes -AS suffix devices -BK suffix devices
TX Yes -AS suffix devices -BK suffix devices
DX Yes -AS suffix devices -BK suffix devices

Section Content
Commitment to Product Security

Level Two Title

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