Intel® Stratix® 10 Device Security User Guide

Download PDF
ID 683642
Date 7/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel Stratix 10 Device Security Overview 2. Authentication and Authorization 3. AES Bitstream Encryption 4. Device Provisioning 5. Advanced Features 6. Intel® Stratix® 10 Device Security User Guide Archives 7. Document Revision History for Intel® Stratix® 10 Device Security User Guide
1. Intel Stratix 10 Device Security Overview x
1.1. Commitment to Product Security
2. Authentication and Authorization x
2.1. Creating a Signature Chain 2.2. Signing a Configuration Bitstream
2.1. Creating a Signature Chain x
2.1.1. Creating Authentication Key Pairs on the Local File System 2.1.2. Creating Authentication Key Pairs in SoftHSM 2.1.3. Creating the Signature Chain Root Entry 2.1.4. Creating a Signature Chain Public Key Entry
2.2. Signing a Configuration Bitstream x
2.2.1. Quartus Key File Assignment 2.2.2. Co-Signing SDM Firmware 2.2.3. Signing Configuration Bitstream Using the quartus_sign Command 2.2.4. Verifying Configuration Bitstream Signature Chains
3. AES Bitstream Encryption x
3.1. Creating the AES Root Key 3.2. Quartus Encryption Settings 3.3. Encrypting a Configuration Bitstream
3.3. Encrypting a Configuration Bitstream x
3.3.1. Configuration Bitstream Encryption Using the Programming File Generator Graphical Interface 3.3.2. Configuration Bitstream Encryption Using the Programming File Generator Command Line Interface 3.3.3. Partially Encrypted Configuration Bitstream Generation Using the Command Line Interface 3.3.4. Partial Reconfiguration Bitstream Encryption
4. Device Provisioning x
4.1. Using SDM Provision Firmware 4.2. Authentication Root Key Provisioning 4.3. Using QSPI Factory Default Helper Image on Owned Devices 4.4. Programming Key Cancellation ID Fuses 4.5. Security Setting Fuse Provisioning 4.6. AES Root Key Provisioning 4.7. Converting Owner Root Key, AES Root Key Certificates, and Fuse files to Jam STAPL File Formats
4.6. AES Root Key Provisioning x
4.6.1. AES Root Key Compact Certificate 4.6.2. Intrinsic ID® PUF AES Root Key Provisioning 4.6.3. Black Key Provisioning
4.6.2. Intrinsic ID® PUF AES Root Key Provisioning x
4.6.2.1. Intrinsic ID PUF Enrollment 4.6.2.2. Wrapping the AES Root Key 4.6.2.3. Programming Helper Data and Wrapped Key to QSPI Flash Memory 4.6.2.4. Querying Intrinsic ID PUF Activation Status 4.6.2.5. Location of the PUF in Flash Memory
4.6.3. Black Key Provisioning x
4.6.3.1. Black Key Provisioning Options
5. Advanced Features x
5.1. Secure Debug Authorization 5.2. HPS Debug Certificates 5.3. Platform Attestation 5.4. Physical Anti-Tamper 5.5. Using Design Security Features with Remote System Update
5.4. Physical Anti-Tamper x
5.4.1. Anti-Tamper Responses 5.4.2. Anti-Tamper Detection 5.4.3. Anti-Tamper Lite Intel® FPGA IP
5.4.3. Anti-Tamper Lite Intel® FPGA IP x
5.4.3.1. Release Information
1. Intel Stratix 10 Device Security Overview
2. Authentication and Authorization
3. AES Bitstream Encryption
4. Device Provisioning
5. Advanced Features
6. Intel® Stratix® 10 Device Security User Guide Archives
7. Document Revision History for Intel® Stratix® 10 Device Security User Guide

4.4. Programming Key Cancellation ID Fuses

Starting with Intel® Quartus® Prime Pro Edition software version 21.1, programming Intel and owner key cancellation ID fuses requires the use of a signed compact certificate. You may sign the key cancellation ID compact certificate with a signature chain that has FPGA section signing permissions. You create the compact certificate with the programming file generator command line tool. You sign the unsigned certificate using the quartus_sign tool or reference implementation.

The following examples create an Intel key cancellation certificate for Intel key ID 7. You may replace 7 with the applicable Intel key cancellation ID from 0-31.

Run the following command to create an unsigned Intel key cancellation ID compact certificate: 
quartus_pfg --ccert -o ccert_type=CANCEL_INTEL_KEY -o cancel_key=7 \
unsigned_cancel_intel7.ccert
Run one of the following commands to sign the unsigned Intel key cancellation ID compact certificate: 
quartus_sign --family=stratix10 --operation=SIGN \
--qky=design0_sign_chain.qky \
--pem=design0_private.pem \
unsigned_cancel_intel7.ccert signed_cancel_intel7.ccert
quartus_sign --family=stratix10 --operation=sign --module=softHSM \
--module_args="--token_label=s10-token \
--user_pin=s10-token-pin \
--hsm_lib=/usr/local/lib/softhsm/libsofthsm2.so" \
--keyname=design0_sign \
--qky=design0_sign_chain.qky \
unsigned_cancel_intel7.ccert signed_cancel_intel7.ccert
Run the following command to create an unsigned owner key cancellation ID compact certificate: 
quartus_pfg --ccert -o ccert_type=CANCEL_OWNER_KEY \
-o cancel_key=2 \
unsigned_cancel_owner2.ccert
Run one of the following commands to sign the unsigned owner key cancellation ID compact certificate: 
quartus_sign --family=stratix10 --operation=SIGN \
--qky=design0_sign_chain.qky \
--pem=design0_private.pem \
unsigned_cancel_owner2.ccert signed_cancel_owner2.ccert
quartus_sign --family=stratix10 --operation=sign --module=softHSM \
--module_args="--token_label=s10-token \
--user_pin=s10-token-pin \
--hsm_lib=/usr/local/lib/softhsm/libsofthsm2.so" \
--keyname=design0_sign \
--qky=design0_sign_chain.qky \
unsigned_cancel_owner2.ccert signed_cancel_owner2.ccert
After you have created a signed key cancellation ID compact certificate, you use the Intel® Quartus® Prime Programmer to program the compact certificate to the device via JTAG. 
//For physical (non-volatile) eFuses 
quartus_pgm -c 1 -m jtag -o "pi;signed_cancel_intel7.ccert" --non_volatile_key 
quartus_pgm -c 1 -m jtag -o “pi;signed_cancel_owner2.ccert” --non_volatile_key 
//For virtual (volatile) eFuses 
quartus_pgm -c 1 -m jtag -o "pi;signed_cancel_intel7.ccert"  
quartus_pgm -c 1 -m jtag -o “pi;signed_cancel_owner2.ccert”

You may additionally send the compact certificate to the SDM using the FPGA or HPS mailbox interface.

Level Two Title