Intel® Stratix® 10 Device Security User Guide

Download PDF
ID 683642
Date 7/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel Stratix 10 Device Security Overview 2. Authentication and Authorization 3. AES Bitstream Encryption 4. Device Provisioning 5. Advanced Features 6. Intel® Stratix® 10 Device Security User Guide Archives 7. Document Revision History for Intel® Stratix® 10 Device Security User Guide
1. Intel Stratix 10 Device Security Overview x
1.1. Commitment to Product Security
2. Authentication and Authorization x
2.1. Creating a Signature Chain 2.2. Signing a Configuration Bitstream
2.1. Creating a Signature Chain x
2.1.1. Creating Authentication Key Pairs on the Local File System 2.1.2. Creating Authentication Key Pairs in SoftHSM 2.1.3. Creating the Signature Chain Root Entry 2.1.4. Creating a Signature Chain Public Key Entry
2.2. Signing a Configuration Bitstream x
2.2.1. Quartus Key File Assignment 2.2.2. Co-Signing SDM Firmware 2.2.3. Signing Configuration Bitstream Using the quartus_sign Command 2.2.4. Verifying Configuration Bitstream Signature Chains
3. AES Bitstream Encryption x
3.1. Creating the AES Root Key 3.2. Quartus Encryption Settings 3.3. Encrypting a Configuration Bitstream
3.3. Encrypting a Configuration Bitstream x
3.3.1. Configuration Bitstream Encryption Using the Programming File Generator Graphical Interface 3.3.2. Configuration Bitstream Encryption Using the Programming File Generator Command Line Interface 3.3.3. Partially Encrypted Configuration Bitstream Generation Using the Command Line Interface 3.3.4. Partial Reconfiguration Bitstream Encryption
4. Device Provisioning x
4.1. Using SDM Provision Firmware 4.2. Authentication Root Key Provisioning 4.3. Using QSPI Factory Default Helper Image on Owned Devices 4.4. Programming Key Cancellation ID Fuses 4.5. Security Setting Fuse Provisioning 4.6. AES Root Key Provisioning 4.7. Converting Owner Root Key, AES Root Key Certificates, and Fuse files to Jam STAPL File Formats
4.6. AES Root Key Provisioning x
4.6.1. AES Root Key Compact Certificate 4.6.2. Intrinsic ID® PUF AES Root Key Provisioning 4.6.3. Black Key Provisioning
4.6.2. Intrinsic ID® PUF AES Root Key Provisioning x
4.6.2.1. Intrinsic ID PUF Enrollment 4.6.2.2. Wrapping the AES Root Key 4.6.2.3. Programming Helper Data and Wrapped Key to QSPI Flash Memory 4.6.2.4. Querying Intrinsic ID PUF Activation Status 4.6.2.5. Location of the PUF in Flash Memory
4.6.3. Black Key Provisioning x
4.6.3.1. Black Key Provisioning Options
5. Advanced Features x
5.1. Secure Debug Authorization 5.2. HPS Debug Certificates 5.3. Platform Attestation 5.4. Physical Anti-Tamper 5.5. Using Design Security Features with Remote System Update
5.4. Physical Anti-Tamper x
5.4.1. Anti-Tamper Responses 5.4.2. Anti-Tamper Detection 5.4.3. Anti-Tamper Lite Intel® FPGA IP
5.4.3. Anti-Tamper Lite Intel® FPGA IP x
5.4.3.1. Release Information
1. Intel Stratix 10 Device Security Overview
2. Authentication and Authorization
3. AES Bitstream Encryption
4. Device Provisioning
5. Advanced Features
6. Intel® Stratix® 10 Device Security User Guide Archives
7. Document Revision History for Intel® Stratix® 10 Device Security User Guide

5.4.1. Anti-Tamper Responses

You enable physical anti-tamper by selecting a response from the Anti-tamper response: dropdown on the Assignments > Device > Device and Pin Options > Security > Anti-Tamper tab. By default, the anti-tamper response is disabled.

Five categories of anti-tamper response are available. When you select your desired response, the options to enable one or more detection methods are enabled.
Figure 15. Available Anti-Tamper Response Options

You may individually select the Enable device self-kill response for each detection method.

If you enable Enable device self-kill response for any detection method, you must also generate a permit kill compact certificate, sign the compact certificate, and program the compact certificate to your device prior to loading a design with the self-kill response enabled.

Use one of the following commands to create a signature chain capable of signing a permit-type compact certificate. Note that permission bit 10 is used in this operation. 

quartus_sign --family=stratix10 --operation=append_key \
--previous_pem=root_private.pem \
--previous_qky=root.qky \
--permission=0x400 \
--cancel=0 \
--input_pem=permit0_sign_public.pem permit0_sign_chain.qky
quartus_sign --family=stratix10 --operation=append_key --module=softHSM \
–module_args="--token_label=s10-token \
--user_pin=s10-token-pin \
--hsm_lib=/usr/local/lib/softhsm/libsofthsm2.so" \
--previous_keyname=root \
--previous_qky=root.qky \
--permission=0x400 \
--cancel=0 \
--input_keyname=permit0_sign permit0_sign_chain.qky
Use the following command to create an unsigned permit kill compact certificate. 
quartus_pfg --ccert –o ccert_type=DEVICE_PERMIT_KILL unsigned_permit_kill.ccert

Use one of the following commands to sign the permit kill compact certificate. 

quartus_sign --family=stratix10 --operation=sign \
--pem=permit0_sign_private.pem \
--qky=permit0_sign_chain.qky \
unsigned_permit_kill.ccert signed_permit_kill.ccert
quartus_sign --family=stratix10 --operation=sign --module=softHSM \
--module_args="--token_label=s10-token \
--user_pin=s10-token-pin \
--hsm_lib=/usr/local/lib/softhsm/libsofthsm2.so" \
--keyname=permit0_sign \
--qky=permit0_sign_chain.qky \
unsigned_permit_kill.ccert signed_permit_kill.ccert
Use the following command to program the compact certificate to your device. 
quartus_pgm –c 1 –m jtag –o "p;signed_permit_kill.ccert"

When you enable an anti-tamper response, you may choose two available SDM dedicated I/O pins to output the tamper event detection and response status using the Assignments > Device > Device and Pin Options > Configuration > Configuration Pin Options window.

Figure 16. Available SDM dedicated I/O Pins for Tamper Event Detection
Level Two Title