Intel® Stratix® 10 Device Security User Guide

ID 683642
Date 7/20/2022

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5.4.3. Anti-Tamper Lite Intel® FPGA IP

The Anti-Tamper Lite Intel FPGA IP, available in the IP catalog in Intel® Quartus® Prime Pro Edition software, facilitates bidirectional communication between your design and the SDM for tamper events.
Figure 20.  Anti-Tamper Lite Intel FPGA IP
The IP provides the following signals that you connect to your design as needed:
Table 6.   Anti-Tamper Lite Intel FPGA IP I/O Signals
Signal Name Direction Description
gpo_sdm_at_event Output

SDM signal to FPGA fabric logic that an SDM has detected a tamper event. The FPGA logic has approximately 5ms to perform any desired cleaning and respond to the SDM via gpi_fpga_at_response_done and gpi_fpga_at_zeroization_done. The SDM proceeds with the tamper response actions when gpi_fpga_at_response_done is asserted or after no response is received in the allotted time.

gpi_fpga_at_event Input

FPGA interrupt to SDM that your designed anti-tamper detection circuitry has detected a tamper event and the SDM tamper response should be triggered.

gpi_fpga_at_response_done Input

FPGA interrupt to SDM that FPGA logic has performed desired cleaning.

gpi_fpga_at_zeroization_done Input

FPGA signal to SDM that FPGA logic has completed any desired zeroization of design data. This signal is sampled when gpi_fpga_at_response_done is asserted.