5.4.3. Anti-Tamper Lite Intel® FPGA IP
SDM signal to FPGA fabric logic that an SDM has detected a tamper event. The FPGA logic has approximately 5ms to perform any desired cleaning and respond to the SDM via gpi_fpga_at_response_done and gpi_fpga_at_zeroization_done. The SDM proceeds with the tamper response actions when gpi_fpga_at_response_done is asserted or after no response is received in the allotted time.
FPGA interrupt to SDM that your designed anti-tamper detection circuitry has detected a tamper event and the SDM tamper response should be triggered.
FPGA interrupt to SDM that FPGA logic has performed desired cleaning.
FPGA signal to SDM that FPGA logic has completed any desired zeroization of design data. This signal is sampled when gpi_fpga_at_response_done is asserted.
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