Intel® Stratix® 10 Device Security User Guide

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ID 683642
Date 11/09/2021
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Document Table of Contents
Document Table of Contents x
1. Intel Stratix 10 Device Security Overview 2. Authentication and Authorization 3. AES Bitstream Encryption 4. Device Provisioning 5. Advanced Features 6. Intel® Stratix® 10 Device Security User Guide Archives 7. Document Revision History for Intel® Stratix® 10 Device Security User Guide
1. Intel Stratix 10 Device Security Overview x
1.1. Commitment to Product Security
2. Authentication and Authorization x
2.1. Creating a Signature Chain 2.2. Signing a Configuration Bitstream
2.1. Creating a Signature Chain x
2.1.1. Creating Authentication Key Pairs on the Local Filesystem 2.1.2. Creating Authentication Key Pairs in SoftHSM 2.1.3. Creating the Signature Chain Root Entry 2.1.4. Creating a Signature Chain Public Key Entry
2.2. Signing a Configuration Bitstream x
2.2.1. Quartus Key File Assignment 2.2.2. Co-Signing SDM Firmware 2.2.3. Configuring Bitstream Signing Using the quartus_sign Command 2.2.4. Verifying Configuration Bitstream Signature Chains
3. AES Bitstream Encryption x
3.1. Creating the AES Root Key 3.2. Quartus Encryption Settings 3.3. Encrypting a Configuration Bitstream
3.3. Encrypting a Configuration Bitstream x
3.3.1. Configuration Bitstream Encryption Using the Programming File Generator Graphical Interface 3.3.2. Configuration Bitstream Encryption Using the Programming File Generator Command Line Interface 3.3.3. Partially Encrypted Configuration Bitstream Generation Using the Command Line Interface 3.3.4. Partial Reconfiguration Bitstream Encryption
4. Device Provisioning x
4.1. Using SDM Provision Firmware 4.2. Authentication Root Key Provisioning 4.3. Programming Key Cancellation ID Fuses 4.4. Security Setting Fuse Provisioning 4.5. AES Root Key Provisioning 4.6. Converting Owner Root Key, AES Root Key Certificates, and Fuse files to Jam STAPL File Formats
4.5. AES Root Key Provisioning x
4.5.1. AES Root Key Compact Certificate 4.5.2. Intrinsic ID® PUF AES Root Key Provisioning 4.5.3. Black Key Provisioning
4.5.2. Intrinsic ID® PUF AES Root Key Provisioning x
4.5.2.1. Intrinsic ID PUF Enrollment 4.5.2.2. Wrapping the AES Root Key 4.5.2.3. Programming Helper Data and Wrapped Key to QSPI Flash Memory 4.5.2.4. Querying Intrinsic ID PUF Activation Status 4.5.2.5. Location of the PUF in Flash Memory
4.5.3. Black Key Provisioning x
4.5.3.1. Black Key Provisioning Options
5. Advanced Features x
5.1. Secure Debug Authorization 5.2. HPS Debug Certificates 5.3. Platform Attestation 5.4. Physical Anti-Tamper 5.5. Using Design Security Features with Remote System Update
5.4. Physical Anti-Tamper x
5.4.1. Anti-Tamper Responses 5.4.2. Anti-Tamper Detection 5.4.3. Anti-Tamper Lite Intel® FPGA IP
5.4.3. Anti-Tamper Lite Intel® FPGA IP x
5.4.3.1. Release Information
1. Intel Stratix 10 Device Security Overview
2. Authentication and Authorization
3. AES Bitstream Encryption
4. Device Provisioning
5. Advanced Features
6. Intel® Stratix® 10 Device Security User Guide Archives
7. Document Revision History for Intel® Stratix® 10 Device Security User Guide

5.2. HPS Debug Certificates

To enable only authorized access to the HPS debug access port (DAP) via JTAG interface, you click the Intel® Quartus® Prime Assignments menu and select Device > Device and Pin Options > Configuration tab, then enable the HPS debug access port (DAP) by selecting either HPS Pins or SDM Pins from the drop down menu, and ensuring the Allow HPS debug without certificates checkbox is not selected.
Figure 13. Specify Either HPS or SDM Pins for the HPS DAP

You then compile and load the design with these settings.

You create a signature chain with the appropriate permissions to sign an HPS debug certificate. 
quartus_sign --family=Stratix10 --operation=append_key \ 
--previous_pem=root_private.pem --previous_qky=root.qky \ 
--permission=0x8 --cancel=1 \ 
hps_debug_cert_public_key.pem hps_debug_cert_sign_chain.qky
You use the Intel® Quartus® Prime Programmer to request an unsigned HPS debug certificate from the device where the debug design is loaded. 
quartus_pgm -c 1 -m jtag -o “e;unsigned_hps_debug.cert;1SX280HH2”
You sign the unsigned HPS debug certificate using the quartus_sign tool or reference implementation and the HPS debug signature chain. 
quartus_sign --family=stratix10 --operation=sign \  
--qky=hps_debug_cert_sign_chain.qky \  
--pem=hps_debug_cert_private_key.pem \  
unsigned_hps_debug.cert signed_hps_debug.cert
You use the Intel® Quartus® Prime Programmer to send the signed HPS debug certificate back to the device to enable access to the HPS DAP. 
quartus_pgm -c 1 -m jtag -o “p;signed_hps_debug.cert"

The HPS debug certificate is only valid from the time it was generated until the next power cycle of the device or until a different type or version of SDM firmware is loaded. You must generate, sign, and program the signed HPS debug certificate, and perform all debug operations, prior to power cycling the device. You may invalidate the signed HPS debug certificate by power cycling the device.

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