Intel® Stratix® 10 Device Security User Guide

ID 683642
Date 11/09/2021

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5.4.2. Anti-Tamper Detection

You may individually enable the frequency, temperature, and voltage detection features of the SDM. FPGA detection depends on including the Anti-Tamper Lite Intel FPGA IP in your design.
Note: SDM frequency and voltage tamper detection methods are dependent on internal references and measurement hardware that can vary across devices. Intel recommends that you characterize the behavior of tamper detection settings.

Frequency tamper detection operates on the configuration clock source. To enable frequency tamper detection, you must specify an option other than Internal Oscillator in the Configuration clock source dropdown on the Assignments > Device > Device and Pin Options > General tab. You must ensure that the Run configuration CPU from internal oscillator checkbox is enabled prior to enabling the frequency tamper detection.

Figure 17. Setting the SDM to Internal Oscillator

To enable frequency tamper detection, select the Enable frequency tamper detection checkbox and select the desired Frequency tamper detection range from the dropdown menu.

Figure 18. Enabling Frequency Tamper Detection

To enable temperature tamper detection, select the Enable temperature tamper detection checkbox and select the desired temperature upper and lower bounds in the corresponding fields. The upper and lower bounds are populated by default with the related temperature range for the device selected in the design.

To enable voltage tamper detection, you select either or both of the Enable VCCL voltage tamper detection or Enable VCCL_SDM voltage tamper detection checkboxes and select the desired Voltage tamper detection trigger percentage in the corresponding field.

Figure 19. Enabling Voltage Tamper Detection