Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata

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ID 683637
Date 6/22/2018
Public
Document Table of Contents
Document Table of Contents x
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata x
Flash Fallback Does Not Meet PCIe Timeout Unsupported Transaction Layer Packet Types JTAG Timing Failures May Be Reported in the FPGA Interface Manager fpgabist Tool Does Not Pass Hexadecimal Bus Numbers Properly Possible Low dma_afu Bandwidth Due to memcpy Function regress.sh -r Option Does Not Work With dma_afu Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata Revision History
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata

JTAG Timing Failures May Be Reported in the FPGA Interface Manager

Description

The Intel® Quartus® Prime Pro Edition Timing Analyzer may report unconstrained JTAG I/O paths in the FIM.

Workaround

These unconstrained paths can be safely ignored because the JTAG I/O paths are not used in the FIM.

Status

Affects: Intel® Acceleration Stack 1.0 Production

Status: Planned fix in Intel® Acceleration Stack 1.1

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