Intel® Stratix® 10 Analog to Digital Converter User Guide

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ID 683612
Date 2/09/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 ADC Overview 2. Intel® Stratix® 10 ADC Architecture and Features 3. Intel® Stratix® 10 ADC Design Considerations 4. Intel® Stratix® 10 ADC Implementation Guides 5. Intel® Stratix® 10 ADC IP Core References 6. Intel® Stratix® 10 Analog to Digital Converter User Guide Archives 7. Document Revision History for the Intel® Stratix® 10 Analog to Digital Converter User Guide
1. Intel® Stratix® 10 ADC Overview x
1.1. Release Information for Voltage Sensor and Temperature Sensor Intel® FPGA IP Cores
2. Intel® Stratix® 10 ADC Architecture and Features x
2.1. Intel® Stratix® 10 Voltage Sensor 2.2. Intel® Stratix® 10 Temperature Sensing Diodes
2.1. Intel® Stratix® 10 Voltage Sensor x
2.1.1. Voltage Conversion
2.2. Intel® Stratix® 10 Temperature Sensing Diodes x
2.2.1. Internal Temperature Sensor 2.2.2. External Temperature Sensor 2.2.3. Temperature Sensor Channels and Locations 2.2.4. Temperature Sensor Error Codes
2.2.1. Internal Temperature Sensor x
2.2.1.1. Temperature Calculation for the Internal Temperature Sensor
3. Intel® Stratix® 10 ADC Design Considerations x
3.1. Guidelines: Selecting Temperature Sensing Chip to Interface with the Intel® Stratix® 10 External TSD 3.2. Guidelines: Using External Temperature Sensors 3.3. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Intel® Stratix® 10 External TSD
4. Intel® Stratix® 10 ADC Implementation Guides x
4.1. Sampling the Intel® Stratix® 10 Voltage Sensor Channels 4.2. Reading the Intel® Stratix® 10 Internal Temperature Sensing Diodes
5. Intel® Stratix® 10 ADC IP Core References x
5.1. Voltage Sensor Intel® FPGA IP Digital Signals 5.2. Temperature Sensor Intel® FPGA IP Digital Signals
1. Intel® Stratix® 10 ADC Overview
2. Intel® Stratix® 10 ADC Architecture and Features
3. Intel® Stratix® 10 ADC Design Considerations
4. Intel® Stratix® 10 ADC Implementation Guides
5. Intel® Stratix® 10 ADC IP Core References
6. Intel® Stratix® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 Analog to Digital Converter User Guide

4.1. Sampling the Intel® Stratix® 10 Voltage Sensor Channels

To sample a single or multiple voltage sensor channels, specify which channels to sample in the Voltage Sensor IP core.
Figure 6. Waveform Example: Sampling Voltage Values from Channels 0, 1, and 3


Note: Set only valid bits in the cmd_data word. Otherwise, the response from the voltage sensor is undefined.
  1. During device initialization, before the device enters user mode:
    • Assert the reset port of the Voltage Sensor IP core to keep it in reset mode.
    • Keep the cmd_valid and cmd_data signal at "0".
  2. After the device enters user mode, simultaneously assert a logic high to the cmd_valid signal and send the cmd_data value. For each sampling, assert cmd_valid for a period of only one to three clock cycles. When you are not acquiring the voltage sensor readout, deassert cmd_valid.
    The cmd_data signal is a 16-bit bitmask that specifies from which channel to sample the voltage. The SDM samples the voltages approximately every 1 ms 1.
    When you assert cmd_valid while cmd_ready is high, the IP core requests from the SDM the most recent voltage values of the channels you specify in cmd_data. After sending the request, the IP core drives cmd_ready low and waits for response from the SDM.
  3. Each time the rsp_valid signal goes high, indicating that the voltage value is ready, read the rsp_data and rsp_channel response signals.
    The rsp_valid signal goes high once for each bit in the cmd_data word. The first valid data in the cycle is available when rsp_valid asserts while the rsp_startofpacket signal is high. The last valid data in the cycle is available when rsp_valid asserts while the rsp_endofpacket signal is high. In each valid response, the rsp_data signal provides the voltage value while the rsp_channel signal indicates from which channel the voltage was sampled.
The value in rsp_data is an unsigned 32-bit fixed point binary number, with 16 bits below the binary point.
Note: For IP core instantiation guidelines, you must refer to the Intel® Stratix® 10 Reset Release IP section in the Intel® Stratix® 10 Configuration User Guide.
Related Information
1 If the SDM processor is busy, the response time may be longer.
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