4.1. Sampling the Intel® Stratix® 10 Voltage Sensor Channels
- During device initialization, before the device enters user mode:
- Assert the reset port of the Voltage Sensor IP core to keep it in reset mode.
- Keep the cmd_valid and cmd_data signal at "0".
- After the device enters user mode, simultaneously assert a logic high to the cmd_valid signal and send the cmd_data value. For each sampling, assert cmd_valid for a period of only one to three clock cycles. When you are not acquiring the voltage sensor readout, deassert cmd_valid.
The cmd_data signal is a 16-bit bitmask that specifies from which channel to sample the voltage. The SDM samples the voltages approximately every 1 ms 1.When you assert cmd_valid while cmd_ready is high, the IP core requests from the SDM the most recent voltage values of the channels you specify in cmd_data. After sending the request, the IP core drives cmd_ready low and waits for response from the SDM.
- Each time the rsp_valid signal goes high, indicating that the voltage value is ready, read the rsp_data and rsp_channel response signals.
The rsp_valid signal goes high once for each bit in the cmd_data word. The first valid data in the cycle is available when rsp_valid asserts while the rsp_startofpacket signal is high. The last valid data in the cycle is available when rsp_valid asserts while the rsp_endofpacket signal is high. In each valid response, the rsp_data signal provides the voltage value while the rsp_channel signal indicates from which channel the voltage was sampled.
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