Intel® Stratix® 10 Analog to Digital Converter User Guide

ID 683612
Date 2/09/2021
Document Table of Contents

4.1. Sampling the Intel® Stratix® 10 Voltage Sensor Channels

To sample a single or multiple voltage sensor channels, specify which channels to sample in the Voltage Sensor IP core.
Figure 6. Waveform Example: Sampling Voltage Values from Channels 0, 1, and 3

Note: Set only valid bits in the cmd_data word. Otherwise, the response from the voltage sensor is undefined.
  1. During device initialization, before the device enters user mode:
    • Assert the reset port of the Voltage Sensor IP core to keep it in reset mode.
    • Keep the cmd_valid and cmd_data signal at "0".
  2. After the device enters user mode, simultaneously assert a logic high to the cmd_valid signal and send the cmd_data value. For each sampling, assert cmd_valid for a period of only one to three clock cycles. When you are not acquiring the voltage sensor readout, deassert cmd_valid.
    The cmd_data signal is a 16-bit bitmask that specifies from which channel to sample the voltage. The SDM samples the voltages approximately every 1 ms 1.
    When you assert cmd_valid while cmd_ready is high, the IP core requests from the SDM the most recent voltage values of the channels you specify in cmd_data. After sending the request, the IP core drives cmd_ready low and waits for response from the SDM.
  3. Each time the rsp_valid signal goes high, indicating that the voltage value is ready, read the rsp_data and rsp_channel response signals.
    The rsp_valid signal goes high once for each bit in the cmd_data word. The first valid data in the cycle is available when rsp_valid asserts while the rsp_startofpacket signal is high. The last valid data in the cycle is available when rsp_valid asserts while the rsp_endofpacket signal is high. In each valid response, the rsp_data signal provides the voltage value while the rsp_channel signal indicates from which channel the voltage was sampled.
The value in rsp_data is an unsigned 32-bit fixed point binary number, with 16 bits below the binary point.
Note: For IP core instantiation guidelines, you must refer to the Intel® Stratix® 10 Reset Release IP section in the Intel® Stratix® 10 Configuration User Guide.
1 If the SDM processor is busy, the response time may be longer.