Low Latency 40-Gbps Ethernet Intel® Stratix® 10 IP Core User Guide

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ID 683600
Date 6/20/2023
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Intel Stratix 10 LL 40GbE IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives 11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device 12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core
1. Datasheet x
1.1. Intel Stratix 10 LL 40GbE IP Core Supported Features 1.2. Intel Stratix 10 LL 40GbE Core Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Intel Stratix 10 LL 40GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Intel Stratix 10 LL 40GbE IP Core Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Intel Stratix 10 LL 40GbE IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Intel Stratix 10 LL 40GbE IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Clock Requirements for 40GBASE-KR4/CR4 Variations 3.5.4. Adding the External TX MAC PLL 3.5.5. Placement Settings for the Intel Stratix 10 LL 40GbE Core
3.6. Intel Stratix 10 LL 40GbE IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Intel Stratix 10 LL 40GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Intel Stratix 10 LL 40GbE Core Functional Description x
4.1.1. Intel Stratix 10 LL 40GbE Core TX MAC Datapath 4.1.2. Intel Stratix 10 LL 40GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Intel® Stratix® 10 Low Latency 40GBASE-KR4 IP Core Variations
4.1.1. Intel Stratix 10 LL 40GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Intel Stratix 10 LL 40GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. Intel® Stratix® 10 LL 40GBASE-KR4/CR4 Registers 7.2. PHY Registers 7.3. TX MAC Registers 7.4. RX MAC Registers 7.5. Statistics Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. Datasheet
2. Intel Stratix 10 LL 40GbE IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device
12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core

11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device

The Intel Stratix 10 LL 40GbE targets an Intel® Stratix® 10 device. However, it is not a straightforward Intel® Stratix® 10 device targeted port of the Low Latency 40GbE IP core that targets an Intel® Arria® 10 device. The signals, registers, and register fields are different: you cannot simply substitute the Intel® Stratix® 10 IP core for the Intel® Arria® 10 or Stratix® V IP core in your design without additional design work.

Table 31.  Major Differences Between the Intel Stratix 10 LL 40GbE IP Core and the Low Latency 40GbE IP Core
The comparison is defined relative to these versions:
  • Intel Stratix 10 LL 40GbE IP core available with the Quartus Prime Pro 17.1 Stratix 10 ES Editions software.
  • Low Latency 40GbE IP core for Intel® Arria® 10 devices, available with the Intel® Quartus® Prime software release v17.0.
This table does not list individual signal name and register differences.

Property

Intel Stratix 10 LL 40GbE IP Core

Low Latency 40GbE IP Core For Arria 10 Device

Device support

Supports Intel® Stratix® 10 device family.

Supports Intel® Arria® 10 device family.

Reset

Provides three asynchronous hard reset signals (general, RX-only, and TX-only) and three soft reset register bits.

Supports single asynchronous hard reset signal and three soft reset register bits.

Client interface width

Avalon® streaming interface 128-bit data bus

Avalon® streaming interface 256-bit data bus or custom streaming interface 128-bit data bus.

Avalon® streaming TX client interface readyLatency Avalon® streaming TX interface readyLatency configurable at 0 or 3 (parameter). Avalon® streaming TX interface readyLatency is always 0.
Preamble passthrough Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP core provides the RX preamble on a separate bus, l2_rx_preamble[63:0]. Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on the TX client interface bus (l4_tx_data or din), and the IP core provides the preamble on the RX client interface bus (l4_rx_data or dout_d).
Interface to transceiver TX PLL You must instantiate a single TX PLL IP core to connect to the single tx_serial_clk input pin of the Intel Stratix 10 LL 40GbE IP core. You can instantiate one to four TX PLL IP cores to connect to the four distinct tx_serial_clk input pins of the LL 40GbE IP core.
Statistics counters Available as a configuration option (parameter). RX and TX statistics counters available independently as two distinct configuration options (parameters).
Statistics counter increment vectors l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled. Individual tx_inc_ and rx_inc_ signals available per possible statistics registers, whether or not statistics registers are enabled.
40GBASE-KR4 Available as a configuration option. Configurable support for 40GBASE-KR4 or 40GBASE-CR4. Implements the IEEE Backplane Ethernet Standard 802.3-2012. 40GBASE-KR4 available as a configuration option. Implements the IEEE Backplane Ethernet Standard 802.3ap-2007.
Flow control Not yet available in this release. Available as a configuration option (parameter).
1588 PTP support Not supported. N/A
Enable alignment of EOP on FCS word Always turned on. Available as a configuration option (parameter).
Minimum average interpacket gap Value is 12 bytes. Values none (single byte), 8 bytes, and 12 bytes available as configuration options (parameter).
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