LVDS SERDES FPGA IP Release Notes

Download PDF
ID 683575
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
LVDS SERDES FPGA IP Release Notes
LVDS SERDES FPGA IP Release Notes x
LVDS SERDES FPGA IP (intel_lvds) v23.2.0 LVDS SERDES Intel FPGA IP (intel_lvds) v23.1.0 LVDS SERDES Intel FPGA IP (intel_lvds) v23.0.0 LVDS SERDES Intel FPGA IP v20.0.1 LVDS SERDES Intel FPGA IP v20.0.0 LVDS SERDES Intel FPGA IP v19.5.0 LVDS SERDES Intel FPGA IP v19.4.0 LVDS SERDES Intel FPGA IP v19.3.0 LVDS SERDES Intel® FPGA IP v18.1 LVDS SERDES Intel® FPGA IP v18.0 Intel® FPGA LVDS SERDES IP Core v17.1 Altera LVDS SERDES IP Core v17.0 Altera LVDS SERDES IP Core v14.1 Altera LVDS SERDES IP Core v14.0 Arria 10 Edition
LVDS SERDES FPGA IP Release Notes

Intel Agilex® 7 F-Series and I-Series General-Purpose I/O User Guide Archives

For the latest and previous versions of this user guide, refer to Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

If an IP version is not listed, the user guide for the previous IP version applies.
Intel® Quartus® Prime Version User Guide
21.2 Intel Agilex General Purpose I/O and LVDS SERDES User Guide
21.1 Intel Agilex General Purpose I/O and LVDS SERDES User Guide
20.3 Intel Agilex General Purpose I/O and LVDS SERDES User Guide
20.2 Intel Agilex General Purpose I/O and LVDS SERDES User Guide
20.1 Intel Agilex General Purpose I/O and LVDS SERDES User Guide
19.4 Intel Agilex General Purpose I/O and LVDS SERDES User Guide
19.3 Intel Agilex General Purpose I/O and LVDS SERDES User Guide
Level Two Title