Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes

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Date 7/08/2017
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1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes
1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes x
1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.1 1.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.0 1.3. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.1 1.4. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Arria 10 Edition
1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes

1.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.0

Table 3.  Version 15.0 May 2015Arria 10 support for this IP core is available in the Altera MegaCore IP Library. Stratix V support is available only through the Self-Service Licensing center.
Description Impact Notes
If you upgrade the LL 40-100GbE IP core to the IP core v15.0, the example design no longer functions correctly. You must regenerate the example design after you upgrade. After you upgrade your IP core, you must regenerate the example design.  
Added optional Synchronous Ethernet support for Arria 10 variations. Turning on the new Enable SyncE parameter adds a new RX recovered clock output signal. Upgrading the IP core to incorporate this feature is optional. This feature does not affect the top-level signals of the IP core unless you turn on the Enable SyncE parameter. If you upgrade, turn on this parameter, and intend to implement a Synchronous Ethernet system, you must reconnect the IP core in your design. Refer to LL 40-100GbE IP Core Signal Changes v15.0 table.
Changed handling of received malformed packets:
  • The IP core asserts the l<n>_rx_error[0] or rx_error[0] signal in the case of an unexpected control character that is not an Error character.
  • Both the LL 40GbE IP core and the LL 100GbE IP core handle received malformed packets the same way.
If you upgrade your IP core to the v15.0 version, you must be aware of this behavior change.  
New output signals explain the control frames that the IP core passes to the RX client interface. The output flags indicate whether the control frame is a standard flow-control frame, a priority-based flow-control frame, or a non-flow control frame. Upgrading the IP core to incorporate this feature is optional. This feature adds top-level output signals to the IP core. Therefore, to utilize this feature after you upgrade, you must reconnect the IP core in your design. Refer to LL 40-100GbE IP Core Signal Changes v15.0 table.
Priority-based flow control is now available for both LL 40GbE IP core variations and LL 100GbE IP core variations. Previously it was available only in LL 100GbE variations. Upgrading the IP core to incorporate this feature is optional. This feature does not affect the top-level signals of the IP core.  
New output status flag indicates when TX lanes are fully aligned and ready to transmit data. Upgrading the IP core to incorporate this feature is optional. This feature adds top-level output signals to the IP core. Therefore, to utilize this feature after you upgrade, you must reconnect the IP core in your design. Refer to LL 40-100GbE IP Core Signal Changes v15.0 table.
New option to direct the IP core to insert an error in a transmitted Ethernet frame. Upgrading the IP core to incorporate this feature is optional. This feature adds top-level input signals to the IP core. Therefore, if you upgrade, you must reconnect the IP core in your design. Refer to LL 40-100GbE IP Core Signal Changes v15.0 table.
The IP core now generates an example project that you can configure on a device, for most variations. The older type of example projects, which you cannot configure on a device, are also generated. Upgrading the IP core to incorporate this feature is optional.  
Minor changes to LL 40GBASE-KR4 feature parameters and registers:
  • Changed default value of link training INITPOSTVAL parameter from 22 to 13.
  • Changed rx_ctle_mode LL 40GBASE-KR4 register field. The IP core uses only the two least significant bits of the 10GBASE-KR register field.
If you upgrade your IP core to the v15.0 version, you must be aware of these changes, and set the parameter and access the register accordingly, in LL 40GBASE-KR4 variations..
Table 4.  LL 40-100GbE IP Core Signal Changes v15.0Signals added or modified in version 15.0.
Old Signal Name New Signal Name Notes
— clk_rx_recover Output RX recovered clock intended to drive the input reference clock of another Ethernet component in a Synchronous Ethernet design. This signal is available if you turn on Enable SyncE in the LL 40-100GbE parameter editor.
— l<n>_rx_status[2:0] (Avalon-ST client interface) New three-bit control frame type flag.
— rx_status[2:0] (custom client interface)
— tx_lanes_stable New output status flag.
— l<n>_tx_error (Avalon-ST client interface) New TX error insertion signal. User logic asserts a bit to direct the IP core to insert an error in the corresponding frame on the Ethernet link.
— tx_error[1:0] or tx_error[3:0] (custom client interface)
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