LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683520
Date 7/13/2021
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Document Table of Contents
Document Table of Contents x
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES IP Core Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Core Initialization and Reset LVDS SERDES IP Core Signals LVDS SERDES IP Core Parameter Settings LVDS SERDES IP Core General Settings LVDS SERDES IP Core Timing LVDS SERDES IP Core Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Core Initialization and Reset x
Initializing the LVDS SERDES IP Core in Non-DPA Mode Initializing the LVDS SERDES IP Core in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES IP Core Parameter Settings x
LVDS SERDES IP Core PLL Settings LVDS SERDES IP Core Receiver Settings LVDS SERDES IP Core Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES IP Core Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES IP Core Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES IP Core Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis for the External PLL Mode Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES IP Core Design Examples x
LVDS SERDES IP Core Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Core Simulation Design Example Combined LVDS SERDES IP Core Transmitter and Receiver Design Example LVDS SERDES IP Core Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Core Signal Interface with LVDS SERDES IP Core IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP Core and LVDS SERDES IP Core in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

LVDS SERDES IP Core Timing

Use the Intel® Quartus® Prime software from version 14.0.a10 onwards to generate the required timing constraint to perform proper timing analysis of the LVDS SERDES IP core in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
Table 16.   LVDS SERDES IP Core Timing Components
Timing Component Description
Source Synchronous Paths The source synchronous paths are paths where clock and data signals are passed from the transmitting devices to the receiving devices. For example:
  • FPGA/LVDS/TX to external receiving device transmitting
  • External transmitting device to FPGA/non-DPA mode/LVDS/RX receiving path
Dynamic Phase Alignment Paths A DPA block registers the I/O capture paths in soft-CDR and DPA-FIFO modes. The DPA block dynamically chooses the best phase from the PLL VCO clocks to latch the input data.
Internal FPGA Paths

The internal FPGA paths are the paths inside the FPGA fabric:

  • LVDS RX hardware to core registers paths
  • Core registers to LVDS TX hardware paths
  • Others core registers to core registers path

The Timing Analyzer reports the corresponding timing margins.

Table 17.   LVDS SERDES Timing Constraint FilesThis table lists the timing files generated by the LVDS SERDES IP core. Use these files for successful timing analysis of the LVDS SERDES IP core. You can find these files in the <variation_name> directory.
File Name Description
<variation_name>_altera_lvds_core20_<quartus_version>_<random_id>.sdc

This .sdc file allows the Intel® Quartus® Prime Fitter to optimize timing margins with timing-driven compilation. The file also allows the Timing Analyzer to analyze the timing of your design.

The IP core uses the .sdc for the following operations:

  • Creating clocks on PLL inputs
  • Creating generated clocks
  • Calling derive_clock_uncertainty
  • Creating proper multi-cycle constraints

You can locate this file in the .qip generated during IP generation.

sdc_util.tcl This .tcl file is a library of functions and procedures that the .sdc uses.
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