Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683517
Date 1/19/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide
1. Introduction x
1.1. Terms and Acronyms 1.2. MCDMA IP Modes
2. Design Example Detailed Description x
2.1. Design Example Overview 2.2. Hardware and Software Requirements 2.3. PIO using MCDMA Bypass Mode 2.4. Avalon-ST Packet Generate/Check 2.5. Avalon-ST Device-side Packet Loopback 2.6. Avalon-MM DMA 2.7. BAM_BAS Traffic Generator and Checker 2.8. External Descriptor Controller
2.1. Design Example Overview x
2.1.1. H-Tile MCDMA IP - Design Examples for Endpoint 2.1.2. P-Tile MCDMA IP - Design Examples for Endpoint 2.1.3. F-Tile MCDMA IP - Design Examples for Endpoint 2.1.4. R-Tile MCDMA IP - Design Examples for Endpoint
2.3. PIO using MCDMA Bypass Mode x
2.3.1. Avalon-ST PIO using MCDMA Bypass Mode 2.3.2. Avalon-MM PIO using MCDMA Bypass Mode
2.3.1. Avalon-ST PIO using MCDMA Bypass Mode x
2.3.1.1. Single-Port Avalon-ST PIO using MCDMA Bypass Mode
2.3.2. Avalon-MM PIO using MCDMA Bypass Mode x
2.3.2.1. Simulation Results 2.3.2.2. Hardware Test Results
2.4. Avalon-ST Packet Generate/Check x
2.4.1. Single-Port Avalon-ST Packet Generate/Check
2.4.1. Single-Port Avalon-ST Packet Generate/Check x
2.4.1.1. Simulation Waveforms 2.4.1.2. Simulation Log 2.4.1.3. Hardware Test Result
2.5. Avalon-ST Device-side Packet Loopback x
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. Avalon-MM DMA x
2.6.1. Simulation Results 2.6.2. Hardware Test Results
2.7. BAM_BAS Traffic Generator and Checker x
2.7.1. BAM_BAS Traffic Generator and Checker Example Design Register Map
2.8. External Descriptor Controller x
2.8.1. Registers 2.8.2. Hardware Test Results
2.8.1. Registers x
2.8.1.1. GCSR Registers (Base address 64’h00000) 2.8.1.2. QCSR Registers(Base address 64’h10000)
3. Design Example Quick Start Guide x
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Intel® Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Intel® Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Intel® Quartus® Prime x
3.2.1. Procedure
3.3. Simulating the Design Example x
3.3.1. Testbench Overview 3.3.2. Supported Simulators 3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.4. Run the Simulation Script 3.3.5. Steps to Run the Simulation 3.3.6. View the Results
3.3.5. Steps to Run the Simulation x
3.3.5.1. Steps to Run the Simulation : QuestaSim* / Questa* Intel® FPGA Edition 3.3.5.2. Steps to Run the Simulation : VCS* / VCS* MX 3.3.5.3. Steps to Run the Simulation : Xcelium*
3.5. Running the Design Example Application on a Hardware Setup x
3.5.1. Program the FPGA 3.5.2. Quick Start Guide
3.5.2. Quick Start Guide x
3.5.2.1. Software Test Setup 3.5.2.2. Driver Support 3.5.2.3. MCDMA Custom Driver 3.5.2.4. MCDMA DPDK Poll Mode Driver 3.5.2.5. MCDMA Kernel Mode Network Device Driver
3.5.2.3. MCDMA Custom Driver x
3.5.2.3.1. Prerequisites 3.5.2.3.2. Software Setup 3.5.2.3.3. Run the Reference Example Application 3.5.2.3.4. Testing Bitstream Configuration beyond 256 Channels (for MCDMA Custom Driver) 3.5.2.3.5. External Descriptor Mode Verification
3.5.2.3.1. Prerequisites x
3.5.2.3.1.1. Configuration Changes from BIOS 3.5.2.3.1.2. External Packages 3.5.2.3.1.3. Set the Boot Parameters
3.5.2.3.2. Software Setup x
3.5.2.3.2.1. Installing the Linux Kernel Driver 3.5.2.3.2.2. Build and Install User Space Library 3.5.2.3.2.3. Enabling VFs and Create Guest VM by Using QEMU 3.5.2.3.2.4. Establish Communication Between Host and QEMU
3.5.2.3.3. Run the Reference Example Application x
3.5.2.3.3.1. Meta Data Test 3.5.2.3.3.2. Custom PIO Read Write Test 3.5.2.3.3.3. BAM Test 3.5.2.3.3.4. BAS Test 3.5.2.3.3.5. Packet Gen Test
3.5.2.4. MCDMA DPDK Poll Mode Driver x
3.5.2.4.1. Prerequisites 3.5.2.4.2. Install PMD and Test Application (for CentOS) 3.5.2.4.3. Install PMD and Test Application (for Ubuntu) 3.5.2.4.4. Create VM Environment 3.5.2.4.5. Run the Reference Example Application
3.5.2.4.1. Prerequisites x
3.5.2.4.1.1. Set the Boot Parameters 3.5.2.4.1.2. Configuration Changes from BIOS 3.5.2.4.1.3. Install and Build Testpmd
3.5.2.4.4. Create VM Environment x
3.5.2.4.4.1. Enable VFs 3.5.2.4.4.2. Create Guest VM by using QEMU 3.5.2.4.4.3. Establish Communication Between Host and VM
3.5.2.4.5. Run the Reference Example Application x
3.5.2.4.5.1. Channel ID VF PF Verification 3.5.2.4.5.2. Example of Verifying on an AVMM Design 3.5.2.4.5.3. Testing Bitstream Configuration beyond 256 Channels (for DPDK Poll Mode Driver) 3.5.2.4.5.4. BAM Test 3.5.2.4.5.5. BAS Test
3.5.2.5. MCDMA Kernel Mode Network Device Driver x
3.5.2.5.1. Build and Install Netdev Driver 3.5.2.5.2. Enable VFs if SRIOV is Supported 3.5.2.5.3. Configure the Number of Channels Supported on the Device 3.5.2.5.4. Configure the MTU Value 3.5.2.5.5. Configure the Device Communication 3.5.2.5.6. Configure Transmit Queue Selection Mechanism 3.5.2.5.7. Test Procedure by Using Name Space Environment 3.5.2.5.8. PIO Test
3.5.2.5.6. Configure Transmit Queue Selection Mechanism x
3.5.2.5.6.1. MCDMA Queue Selection 3.5.2.5.6.2. Transmit Packet Steering (XPS) 3.5.2.5.6.3. Default
1. Introduction
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide

2.8.1.2. QCSR Registers(Base address 64’h10000)

This space contains control and status registers for external descriptor controller. Host maintains separate descriptor ring for both D2H & H2D queues. External descriptor controller example design supports 16 channels. Descriptor context for each channel can be updates in the following CSR registers.

Address [11:8] = Channel number (Queue ID).

Address [7] = Data Mover direction. 0 = D2H, 1 = H2D.

Address [6:3] = Register offset.

Table 21.  D2H Start Address (Offset 8’h00)
Bit[63:0] Name R/W Default Description

[63:0]

Start_addr

R/W

0

D2H ring buffer start address [63:0].
Table 22.  D2H Buffer Size (Offset 8’h08)
Bit[63:0] Name R/W Default Description
[63:16] rsvd     Reserved

[15:0]

size

R/W

0

D2H ring buffer size
Table 23.  D2H Tail Pointer (Offset 8’h10)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

    

Reserved

[15:0]

tail_ptr

R/W

0

D2H ring buffer tail pointer, Updated by Host SW & Read-only for DMA HW.
Table 24.  D2H Head Pointer (Offset 8’h18)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

    

Reserved

[15:0]

head_ptr

RO

0

D2H ring buffer head pointer, Updated by DMA HW & Read-only for Host SW.
Table 25.  D2H Write back Address (Offset 8’h20)
Bit[63:0] Name R/W Default Description

[63:0]

wb_addr

R/W

0

D2H write back address [63:0].
Table 26.  D2H Completion Pointer (Offset 8’h28)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

    

Reserved

[15:0]

cmpl_ptr

RO

0

D2H ring buffer completion pointer, Updated by DMA HW & Read-only for Host SW.
Table 27.  H2D Start address (Offset 8’h80)
Bit[63:0] Name R/W Default Description

[63:0]

Start_addr

R/W

0

H2D ring buffer start address [63:0].
Table 28.  H2D Buffer Size (Offset 8’h88)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

    

Reserved

[15:0]

size

R/W

0

H2D ring buffer size
Table 29.  H2D Tail Pointer (Offset 8’h90)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

    

Reserved

[15:0]

tail_ptr

R/W

0

H2D ring buffer tail pointer, Updated by Host SW & Read-only for DMA HW.
Table 30.  H2D Head Pointer (Offset 8’h98)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

    

Reserved

[15:0]

head_ptr

RO

0

H2D ring buffer head pointer, Updated by DMA HW & Read-only for Host SW.
Table 31.  H2D Write back address (Offset 8’hA0)
Bit[63:0] Name R/W Default Description

[63:0]

wb_addr

R/W

0

H2D write back address [63:0].
Table 32.  H2D Completion Pointer (Offset 8’hA8)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

    

Reserved

[15:0]

cmpl_ptr

RO

0

H2D ring buffer completion pointer, Updated by DMA HW & Read-only for Host SW.
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