V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

The Write Data Mover module fetches data from the Avalon-MM address space using this interface before issuing memory write requests to transfer data to PCIe* system memory.

DMA Write 256-Bit Avalon-MM Master Interface

Signal Name

Direction

Description

WrDMARead_o

Output

When asserted, indicates that the Write DMA module is reading data from a memory component in the Avalon-MM address space to write to the PCIe address space.

WrDmaAddress_o[63:0]

Output

Specifies the address for the data to be read from a memory component in the Avalon-MM address space .

WrDmaReadData_i[127 or 255:0]

Input

Specifies the completion data that the Write DMA module writes to the PCIe address space.

WrDmaBurstCount_o[4:0]or[5:0]

Output

Specifies the burst count in 128- or 256-bit words. This bus is 5 bits for the 256-bit interface. It is 6 bits for the 128-bit interface

WrDmaWaitRequest_i

Input

When asserted, indicates that the memory is not ready to be read.

WrDmaReadDataValid_i

Input

When asserted, indicates that WrDmaReadData_i is valid.

Write DMA Avalon-MM Master Reads Data from FPGA Memory

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