V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

Dynamic reconfiguration compensates for variations due to process, voltage and temperature (PVT). Among the analog settings that you can reconfigure are V OD, pre-emphasis, and equalization.

You can use the Intel Transceiver Reconfiguration Controller to dynamically reconfigure analog settings. For more information about instantiating the Intel Transceiver Reconfiguration Controller IP core refer to Hard IP Reconfiguration .

Transceiver Control SignalsIn this table, <n> is the number of interfaces required.

Signal Name

Direction

Description

reconfig_from_xcvr[(<n>46)-1:0]

Output

Reconfiguration signals to the Transceiver Reconfiguration Controller.

reconfig_to_xcvr[(<n>70)-1:0]

Input

Reconfiguration signals from the Transceiver Reconfiguration Controller.

reconfig_clk_locked

Output

When asserted, indicates that the PLL that provides the fixed clock required for transceiver initialization is locked. The Application Layer should be held in reset until reconfig_clk_locked is asserted.

The following table shows the number of logical reconfiguration and physical interfaces required for various configurations. The Quartus® Prime Fitter merges logical interfaces to minimize the number of physical interfaces configured in the hardware. Typically, one logical interface is required for each channel and one for each PLL. The ×8 variants require an extra channel for PCS clock routing and control. The ×8 variants use channel 4 for clocking.

Number of Logical and Physical Reconfiguration Interfaces

Variant

Logical Interfaces

Gen2 ×4

5

Gen1 and Gen2 ×8

10

Gen3 ×4

6

Gen3 ×8

11

For more information about the Transceiver Reconfiguration Controller, refer to the Transceiver Reconfiguration Controller chapter in the Intel Transceiver PHY IP Core User Guide .

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