V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

The Read Descriptor Controller Avalon-MM master interface drives the non-bursting Avalon-MM slave interface. The Read Descriptor Controller uses this interface to write descriptor status to the PCIe domain and possibly to MSI when MSI messages are enabled. This Avalon-MM master interface is only available for variants with the internally instantiated Descriptor Controller.

By default MSI interrupts are enabled. You specify the Number of MSI messages requested on the MSI tab of the parameter editor. The MSI Capability Structure is defined in Section 6.8.1 MSI Capability Structure of the PCI Local Bus Specification.

Read Descriptor Controller Avalon-MM Master interface

Signal Name

Direction

Description

RdDCMAddress_o[63:0]

Output

Specifies the descriptor status table or MSI address.

RdDCMByteEnable_o[3:0]

Output

Specifies which data bytes are valid.

RdDCMReadDataValid_i

Input

When asserted, indicates that the read data is valid.

RdDCMReadData_i[31:0]

Input

Specifies the read data of the descriptor status table entry addressed.

RdDCMRead_o

Output

When asserted, indicates a read transaction. Currently, this is a write-only interface so that this signal never asserts.

RdDCMWaitRequest_i

Input

When asserted, indicates that the connected Avalon-MM slave interface is busy and cannot accept a transaction.

RdDCMWriteData_o[31:0]

Output

Specifies the descriptor status or MSI data..

RdDCMWrite_o

Output

When asserted, indicates a write transaction.

Did you find the information on this page useful?

Characters remaining:

Feedback Message