V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

The TX Slave module translates Avalon-MM read and write requests to PCI Express TLPs.

The slave module supports a single outstanding non-bursting request. It typically sends status updates to the host. This is a 32-bit Avalon-MM slave interface.

TX Slave Control

Signal Name

Direction

Description

TxsChipSelect_i

Input

When asserted, indicates that this slave interface is selected. When txs_chipselect_i is deasserted, txs_read_i and txs_write_i signals are ignored.

TxsRead_i

Input

When asserted, specifies a Avalon-MM Ignored when the chip select is deasserted.

TxsWrite_i

Input

When asserted, specifies a Avalon-MM Ignored when the chip select is deasserted.

TxsWriteData_i[31:0]

Input

Specifies the Avalon-MM data for a write command.

TxsAddress_i[<w>-1:0]

Input

Specifies the Avalon-MM byte address for the read or write command. The width of this address bus is specified by the parameter Address width of accessible PCIe memory space.

TxsByteEnable_i[3:0]

Input

Specifies the valid bytes for a write command.

TxsReadData_o[31:0]

Output

Drives the read completion data.

TxsReadDataValid_o

Output

When asserted, indicates that read data is valid.

TxsWaitRequest_o

Output

When asserted, indicates that the Avalon-MM slave port is not ready to respond to a read or write request.

The non-bursting Avalon-MM slave may assertTxsWaitRequest_o during idle cycles. An Avalon-MM master may initiate a transaction when TxsWaitRequest_o is asserted and wait for that signal to be deasserted.

Non-Bursting Slave Interface Sends Status to Host

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