V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

The MSI interrupt notifies the host when a DMA operation has completed. After the host receives this interrupt, it can poll the DMA read or write status table to determine which entry or entries have the done bit set. This mechanism allows host software to avoid continuous polling of the status table done bits. Use this interface to receive information required to generate MSI or MSI-X interrupts to the Root Port via the TX Slave interface.

MSI Interrupt

Signal

Direction

Description

MSIIntfc_o[81:0]

Output

This bus provides the following MSI address, data, and enabled signals:

  • MSIIntfc_o[81]: Master enable
  • MSIIntfc_o[80]: MSI enable
  • MSIIntfc_o[79:64]: MSI data
  • MSIIntfc_o[63:0]: MSI address

MSIXIntfc_o[15:0]

Output

Provides for system software control of MSI-X as defined in Section 6.8.2.3 Message Control for MSI-X in the PCI Local Bus Specification, Rev. 3.0. The following fields are defined:

  • MSIXIntfc_o[15]: Enable
  • MSIXIntfc_o[14]: Mask
  • MSIXIntfc_o[13:11]: Reserved
  • MSIXIntfc_o[10:0]: Table size
MSIControl_o[15:0]

Output

Provides system software control of the MSI messages as defined in Section 6.8.1.3 Message Control for MSI in the PCI Local Bus Specification, Rev. 3.0. The following fields are defined:

  • MSIControl_o[15:9]: Reserved
  • MSIControl_o[8]: Per-Vector Masking Capable
  • MSIControl_o[7]: 64-Bit Address Capable
  • MSIControl_o[6:4]: Multiple Message Enable
  • MSIControl_o[3:1]: MSI Message Capable
  • MSIControl_o[0]: MSI Enable

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