V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

The CRA interface provides access to the control and status registers of the Avalon-MM bridge. This interface has the following properties:

  • 32-bit data bus
  • Supports a single transaction at a time
  • Supports single-cycle transactions (no bursting)
Note: When the Avalon® -MM Hard IP for PCIe IP Core is in Root Port mode, and the application logic issues a CfgWr or CfgRd via the CRA interface, it needs to fill the Tag field in the TLP Header with the value 0x10 to ensure that the corresponding Completion gets routed to the CRA interface correctly. If the application logic sets the Tag field to some other value, the Avalon® -MM Hard IP for PCIe IP Core does not overwrite that value with the correct value.
Avalon-MM CRA Slave Interface Signals

Signal Name

Direction

Description

CraRead_i

Input

Read enable.

CraWrite_i

Input

Write request.

CraAddress_i[13:0]

Input

An address space of 16 KB is allocated for the control registers. Avalon® -MM slave addresses provide address resolution down to the width of the slave data bus. Because all addresses are byte addresses, this address logically goes down to bit 2. Bits 1 and 0 are 0. To read or write individual bytes of a DWORD, use byte enables. For example, to write bytes 0 and 1, set this signal to 4'b0011.

An address space of 32 KB is allocated for the control registers. Avalon® -MM slave addresses provide address resolution down to the width of the slave data bus. Because all addresses are byte addresses, this address logically goes down to bit 2. Bits 1 and 0 are 0. To read or write individual bytes of a DWORD, use byte enables. For example, to write bytes 0 and 1, set this signal to 4'b0011.

CraWriteData_i[31:0]

Input

Write data. The current version of the CRA slave interface is read-only. Including this signal as part of the Avalon-MM interface, makes future enhancements possible.

CraReadData_o[31:0]

Output

Read data lines.

CraByteEnable_i[3:0]

Input

Byte enable.

CraWaitRequest_o

Output

Wait request to hold off additional requests.

CraChipSelect_i

Input

Chip select signal to this slave.

CraIrq_o

Output

Interrupt request. A port request for an Avalon-MM interrupt.

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