R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/04/2023
Public
Document Table of Contents

3.3. TLP Bypass Mode

The R-Tile Avalon® -ST IP for PCIe includes a TLP Bypass mode for both downstream and upstream ports to allow the implementation of advanced features such as:
  • The upstream port or the downstream port of a switch.
  • A custom implementation of a Transaction Layer to meet specific user requirements.
Table 41.  Supported TLP Bypass Configurations UP = upstream port; DN = downstream port
IP Mode Port Mode
X16

UP

DN

X8/X8

UP/UP

UP/DN

DN/UP

DN/DN

X4/X4/X4/X4

UP/UP/UP/UP

DN/DN/DN/DN