Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.15. SR-IOV Virtualization Extended Capabilities Registers

Figure 28. SR-IOV Virtualization Extended Capabilities Registers
Table 67.   SR-IOV Virtualization Extended Capabilities Registers

Address (hex)

Name

Description

Alternative RID (ARI) Capability Structure

Single-Root I/O Virtualization (SR-IOV) Capability Structure

0x240

SR-IOV Extended Capability Header

PCI Express Extended Capability ID for SR-IOV and next capability pointer.

0x244

SR-IOV Capabilities Register

Lists supported capabilities of the SR-IOV implementation.

0x248

SR-IOV Control and Status Registers

The lower 16 bits implement the SR-IOV Control Register. The upper 16 bits implement the SR-IOV Status Register.

0x24C

InitialVFs/TotalVFs

The lower 16 bits specify the initial number of VFs attached to PF0. The upper 16 bits specify the total number of PFs available for attaching to PF0.

0x250

Function Dependency Link, NumVFs

The Function Dependency field describes dependencies between Physical Functions. The NumVFs field contains the number of VFs currently configured for use.

0x0254

VF Offset/Stride

Specifies the offset and stride values used to assign routing IDs to the VFs.

0x198

VF Device ID

Specifies VF Device ID assigned to the device.

0x25C

Supported Page Sizes

Specifies all page sizes supported by the device.

0x260

System Page Size

Stores the page size currently selected.

0x264

VF BAR 0

VF Base Address Register 0. Can be used independently as a 32-bit BAR, or combined with VF BAR 1 to form a 64-bit BAR.

0x268

VF BAR 1

VF Base Address Register 1. Can be used independently as a 32-bit BAR, or combined with VF BAR 0 to form a 64-bit BAR.

0x26C

VF BAR 2

VF Base Address Register 2. Can be used independently as a 32-bit BAR, or combined with VF BAR 3 to form a 64-bit BAR.

0x270

VF BAR 3

VF Base Address Register 3. Can be used independently as a 32-bit BAR, or combined with VF BAR 2 to form a 64-bit BAR.

0x274

VF BAR 4

VF Base Address Register 4. Can be used independently as a 32-bit BAR, or combined with VF BAR 5 to form a 64-bit BAR.

0x278

VF BAR 5

VF Base Address Register 5. Can be used independently as a 32-bit BAR, or combined with VF BAR 4 to form a 64-bit BAR.

0x27C

VF Migration State Array Offset

Not implemented.

Secondary PCI Express Extended Capability Structure (Gen3, PF 0 only)

0x300

Secondary PCI Express Extended Capability Header

PCI Express Extended Capability ID for Secondary PCI Express Capability, and next capability pointer.

0x304

Link Control 3 Register

Not implemented.

0x308

Lane Error Status Register

Per-lane error status bits.

0x30C

Lane Equalization Control Register 0

Transmitter Preset and Receiver Preset Hint values for Lanes 0 and 1 of remote device. These values are captured during Link Equalization.

0x310

Lane Equalization Control Register 1

Transmitter Preset and Receiver Preset Hint values for Lanes 2 and 3 of remote device. These values are captured during Link Equalization.

0x314

Lane Equalization Control Register 2

Transmitter Preset and Receiver Preset Hint values for Lanes 4 and 5 of remote device. These values are captured during Link Equalization.

0x318

Lane Equalization Control Register 3

Transmitter Preset and Receiver Preset Hint values for Lanes 6 and 7 of remote device. These values are captured during Link Equalization.

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