Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

D.1. SR-IOV PCIe Revision History

Date

Version Changes Made
2016.05.02 16.0 Removed support for the 128-bit interface to the Application Layer.

Changed addresses for the following registers:

  • ARI
  • Uncorrectable Error Mask Resgister
  • Uncorrectable Error Severity Register
  • Correctable Error Status Register
  • Correctable Error Mask Register
  • Advanced Error Capabilities and Control Register
  • Header Log Registers 0-3
  • SR-IOV Virtualization Extended Capabilities Registers
  • Secondary PCI Express Extended Capability Header
  • Lane Error Status Registers
2015.11.30 15.1
  • Changed support for 128-bit interface to the Application Layer to preliminary.
  • Corrected instructions for switching between serial and PIPE simulation.
  • Revised discussion on possible conflict between LMI writes and Host writes to the Configuration Space.
  • Added definitions for the following optional signals:
    • tx_st_parity
    • rx_st_parity
    • tx_con_cred_sel
  • Fixed minor errors and typos.
2014.12.15 14.1 Made the following changes to the user guide:
  • Corrected definition of app_int_sts_fn. This signal is not a vector.
  • Corrected definition of rx_st_err. This signal is not a vector.
  • Added vector to descriptions of ko_clp_spc_data[11:0] and ko_cpl_spc_header[7:0].
  • Removed fixedclk_locked signal.
  • Added instructions to run ModelSim simulation.
  • Added statement about running gate-level simulation.
  • Added resource utilization to Datasheet chapter.
2014.06.30 14.0 Initial Release

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