Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

Clock Summary

Name

Frequency

Clock Domain

coreclkout_hip

62.5, 125 or 250 MHz

Avalon‑ST interface between the Transaction and Application Layers.

pld_clk

125 or 250 MHz

Application and Transaction Layers.

refclk

100 or 125 MHz

SERDES (transceiver). Dedicated free running input clock to the SERDES block.

reconfig_xcvr_clk

100 –125 MHz

Transceiver Reconfiguration Controller.

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