Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

4.3. Avalon‑ST RX Interface

Table 24.  Avalon-ST RX Datapath

Signal

Direction

Description

rx_st_data[255:0]

Output

Receive data bus. Refer to figures following this table for the mapping of the Transaction Layer’s TLP information to rx_st_data and examples of the timing of this interface. Note that the position of the first payload dword depends on whether the TLP address is qword aligned. The mapping of message TLPs is the same as the mapping of TLPs with 4‑dword headers.

rx_st_sop

Output

Indicates that this is the first cycle of the TLP when rx_st_valid is asserted.

rx_st_eop

Output

Indicates that this is the last cycle of the TLP when rx_st_valid is asserted.

rx_st_ready

Input

Indicates that the Application Layer is ready to accept data. The Application Layer deasserts this signal to throttle the data stream.

If rx_st_ready is asserted by the Application Layer on cycle <n> , then <n + > readyLatency is a ready cycle, during which the Transaction Layer may assert valid and transfer data.

The RX interface supports a readyLatency of 2 cycles.

rx_st_valid

Output

Clocks rx_st_data into the Application Layer. Deasserts within 2 clocks of rx_st_ready deassertion and reasserts within 2 clocks of rx_st_ready assertion if more data is available to send.

rx_st_parity[31:0]

Output

The IP core generates byte parity when you turn on Enable byte parity ports on Avalon-ST interface on the System Settings tab of the parameter editor. Each bit represents odd parity of the associated byte of the rx_st_data bus. For example, bit[0] corresponds to rx_st_data[7:0], bit[1] corresponds to rx_st_data[15:8], and so on.
rx_st_empty[1:0] Output

Indicates the number of quadwords that are empty during cycles that contain the end of a packet. Its encodings are defined:

  • 00: Data on rx_st_data_app[255:0] is valid. If the TLP is ending in this cycle, its last byte is in rx_st_data_ app[255:192].
  • 01: Data on rx_st_data_app[191:0] is valid. A TLP is ending in this cycle, and its last byte is in rx_st_data_ app[191:128].
  • 10: Data on rx_st_data_app[127:0] is valid. A TLP is ending in this cycle, and its last byte is in rx_st_data_ app[127:64] .
  • 11: Data on rx_st_data_app[63:0] is valid. A TLP is ending in this cycle, and its last byte is in rx_st_data_ app[63:0] .
rx_st_err Output When asserted, indicates an uncorrectable error in the TLP being transferred.

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