40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes

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ID 683484
Date 6/15/2022
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Product Discontinuance Notification 1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes
1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes x
1.1. 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.1 1.2. 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Update 2 1.3. 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 1.4. 40- and 100-Gbps Ethernet MAC and PHY IP Core v13.1 1.5. 40- and 100-Gbps Ethernet MAC and PHY IP Core v13.0 1.6. 40- and 100-Gbps Ethernet MAC and PHY IP Core v12.1
Product Discontinuance Notification
1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes

1.4. 40- and 100-Gbps Ethernet MAC and PHY IP Core v13.1

Table 4.  Version 13.1 November 2013
Description Impact Notes
Added 40GBASE-KR4 option with FEC and with auto-negotiation and link training mode options. – –
Added Synchronous Ethernet clock support option in Stratix V devices. The option separates the TX PLL and RX CDR input reference clocks (tx_ref_clk and rx_ref_clk signals replace ref_clk for these variations) and exposes the RX recovered clock. – –
Exposed link fault signals remote_fault_status and local_fault_status in duplex variations. – –
Exposed PHY status signals tx_lanes_stable and lanes_deskewed in MAC and PHY variations. – –
Updated and simplified the example design and testbench. The testbench stimulus is simpler and the user no longer needs to configure the DUT with a specific name and clock rate. – –
Level Two Title