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1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices
4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices
4.3. Setting Up the Motor Control Board with your Development Board
4.4. Programming the Hardware onto the Device
4.5. Setting Up Terminal Emulator
4.6. Downloading the HPS Software to the Device
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example
6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example
6.3. Vibration Suppression Tab
6.4. Controlling the DC-DC Converter
6.5. Tuning the PI Controller Gains
6.6. Controlling the Speed and Position Demonstrations
6.7. Monitoring Performance
9.1. Processor Subsystem
9.2. Six-channel PWM Interface
9.3. DC Link Monitor
9.4. Drive System Monitor
9.5. Quadrature Encoder Interface
9.6. Sigma-Delta ADC Interface for Drive Axes
9.7. DC-DC Converter
9.8. Motor Control Modes
9.9. FOC Subsystem
9.10. FFTs
9.11. DEKF Technique for Battery Management
9.12. Signals
9.13. Registers
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
9.9.2. Avalon Memory-Mapped Interface
9.9.3. About DSP Builder for Intel FPGAs
9.9.4. DSP Builder for Intel FPGAs Folding
9.9.5. DSP Builder for Intel FPGAs Model Resource Usage
9.9.6. DSP Builder for Intel FPGAs Design Guidelines
9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
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Compiling the Design
Either compile your design or use the Intel-provided pre-compiled .sof from the master_image directory of your reference design variant.
- By default, Intel configures <variant> .v for EnDat encoders for FalconEye 2 HSMC Motor Control Board projects; BiSS for all Multiaxis Motor Control Board projects. In <variant> .v, to use BiSS, add the following line; to use EnDat, remove it (if present).
"define BISS"
- Add the paths to the license files for the EnDat and BiSS IP components to the Quartus II license path.
- Click Tools > License Setup.
- Copy any existing license paths into a text editor.
- Browse to the EnDat license file ip\endat_OCP\dsgn\vhdl_ava_ALT_enc_ocp\ocp _license.dat and click Open.
- Copy and paste this license path into your text editor. Add a semicolon to separate this text from the original text.
- Browse to the BiSS license file ip\biss_OCP\license.dat and click Open.
- Copy and paste this license path into your text editor. Add a semicolon to separate this text from the original text and teh EnDat license.
- Copy and paste the text from the text editor to the Quartus II License File dialog box.
The final license path is <Project directory>\ip\endat_OCP\dsgn\vhdl_ava_ALT_enc_ocp; <Project directory>\ip\biss_OCP\license.dat;<original license paths>. Alternatively, you can add this path to the Windows environment variable LM_LICENSE_FILE.
- Click Processing > Start Compilation .
Note: You may edit the reference design project in Qsys.